drm/amd/display: add MPC MCM 1D LUT clock gating programming

Missing clock gating programming blocks memory power on from boot up.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
index 994b21ed272f175318a0b3295ac1c1e052a6b95d..e789e654c38705116bd70f7b023f7b44cf8b1ba9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
@@ -71,12 +71,13 @@ void mpc32_power_on_blnd_lut(
 {
        struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 
+       REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);
+
        if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
                if (power_on) {
                        REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
                        REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
                } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
-                       ASSERT(false);
                        /* TODO: change to mpc
                         *  dpp_base->ctx->dc->optimized_required = true;
                         *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 1a0ed1c7e2d456ed2093f9a76424d61f93f4464b..13324422ff50e37b45aae18979dfa61434d89445 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -736,7 +736,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .i2c = true,
                        .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
                        .dscl = true,
-                       .cm = false,
+                       .cm = true,
                        .mpc = true,
                        .optc = true,
                        .vpg = true,