&cp0_sata0 {
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_usb3_0 {
&cp1_sata0 {
pinctrl-0 = <&cp0_pci1_reset_pins>;
status = "okay";
+
+ sata-port@1 {
+ phys = <&cp1_comphy0 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_mdio {
/* CON4 on CP0 expansion */
&cp0_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp0_comphy1 0>;
+ phy-names = "cp0-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp0_comphy3 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
/* CON9 on CP0 expansion */
/* CON4 on CP1 expansion */
&cp1_sata0 {
status = "okay";
+
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
/* CON9 on CP1 expansion */
};
&cp0_sata0 {
- /* CPM Lane 0 - U29 */
status = "okay";
+
+ /* CPM Lane 5 - U29 */
+ sata-port@1 {
+ phys = <&cp0_comphy5 1>;
+ phy-names = "cp0-sata0-1-phy";
+ };
};
&cp0_sdhci0 {
};
&cp1_sata0 {
+ status = "okay";
+
/* CPS Lane 1 - U32 */
+ sata-port@0 {
+ phys = <&cp1_comphy1 0>;
+ phy-names = "cp1-sata0-0-phy";
+ };
+
/* CPS Lane 3 - U31 */
- status = "okay";
+ sata-port@1 {
+ phys = <&cp1_comphy3 1>;
+ phy-names = "cp1-sata0-1-phy";
+ };
};
&cp1_spi1 {
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+ };
};
CP110_LABEL(xor0): xor@6a0000 {