arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
authorMiquel Raynal <miquel.raynal@bootlin.com>
Wed, 31 Jul 2019 12:21:23 +0000 (14:21 +0200)
committerGregory CLEMENT <gregory.clement@bootlin.com>
Tue, 27 Aug 2019 14:17:28 +0000 (16:17 +0200)
Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
arch/arm64/boot/dts/marvell/armada-7040-db.dts
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
arch/arm64/boot/dts/marvell/armada-8040-db.dts
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
arch/arm64/boot/dts/marvell/armada-cp110.dtsi

index f34ee87a0f569e1fecab273a28c01b0ccd1e0b49..45eb4197e603278145fa3b8d618cfa9540f5b7a9 100644 (file)
 
 &cp0_sata0 {
        status = "okay";
+
+       sata-port@1 {
+               phys = <&cp0_comphy3 1>;
+               phy-names = "cp0-sata0-1-phy";
+       };
 };
 
 &cp0_usb3_0 {
index f275d9420d5be9c68fb003a37b56f9c8270145bb..1527c82177ab4f8bcd35e9aaa85fbb69e098e5a2 100644 (file)
 &cp1_sata0 {
        pinctrl-0 = <&cp0_pci1_reset_pins>;
        status = "okay";
+
+       sata-port@1 {
+               phys = <&cp1_comphy0 1>;
+               phy-names = "cp1-sata0-1-phy";
+       };
 };
 
 &cp1_mdio {
index d6e9c014c2f98a9834fcd93dfc534631e7e39342..66afed6c6245f0b7e40d21ad13363acdeb99cacb 100644 (file)
 /* CON4 on CP0 expansion */
 &cp0_sata0 {
        status = "okay";
+
+       sata-port@0 {
+               phys = <&cp0_comphy1 0>;
+               phy-names = "cp0-sata0-0-phy";
+       };
+       sata-port@1 {
+               phys = <&cp0_comphy3 1>;
+               phy-names = "cp0-sata0-1-phy";
+       };
 };
 
 /* CON9 on CP0 expansion */
 /* CON4 on CP1 expansion */
 &cp1_sata0 {
        status = "okay";
+
+       sata-port@0 {
+               phys = <&cp1_comphy1 0>;
+               phy-names = "cp1-sata0-0-phy";
+       };
+       sata-port@1 {
+               phys = <&cp1_comphy3 1>;
+               phy-names = "cp1-sata0-1-phy";
+       };
 };
 
 /* CON9 on CP1 expansion */
index 205071b45a324988ed140c44204850d37a9a4843..b8f28d62be5cc04a576134a33f2361a8652fa7b5 100644 (file)
 };
 
 &cp0_sata0 {
-       /* CPM Lane 0 - U29 */
        status = "okay";
+
+       /* CPM Lane 5 - U29 */
+       sata-port@1 {
+               phys = <&cp0_comphy5 1>;
+               phy-names = "cp0-sata0-1-phy";
+       };
 };
 
 &cp0_sdhci0 {
 };
 
 &cp1_sata0 {
+       status = "okay";
+
        /* CPS Lane 1 - U32 */
+       sata-port@0 {
+               phys = <&cp1_comphy1 0>;
+               phy-names = "cp1-sata0-0-phy";
+       };
+
        /* CPS Lane 3 - U31 */
-       status = "okay";
+       sata-port@1 {
+               phys = <&cp1_comphy3 1>;
+               phy-names = "cp1-sata0-1-phy";
+       };
 };
 
 &cp1_spi1 {
index 711f380293115d79f589aa13821acb148ec65152..d81944902650257ded56789c052e783179e606a0 100644 (file)
                        interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&CP110_LABEL(clk) 1 15>,
                                 <&CP110_LABEL(clk) 1 16>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                        status = "disabled";
+
+                       sata-port@0 {
+                               reg = <0>;
+                       };
+
+                       sata-port@1 {
+                               reg = <1>;
+                       };
                };
 
                CP110_LABEL(xor0): xor@6a0000 {