wifi: rtw89: 8852b: set proper configuration before loading NCTL

Before loading RF NCTL table, we need to configure IQK/DPK clock and reset
them, and then polling NCTL state ready. Since 8852BE needs additional
one setting, add it by this patch. Also, give them proper names.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221005083212.45683-4-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index d9c4debecc62272f7b61bd8b4a71337d38d80a62..fb7872225ee3d9adfe6acd19f148e0c3cf7c9953 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -1368,13 +1368,15 @@ static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
        int ret;
 
        /* IQK/DPK clock & reset */
-       rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3);
-       rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1);
-       rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000);
-       rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000);
+       rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
+       rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
+       rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
+       rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
+       if (chip->chip_id == RTL8852B)
+               rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
 
        /* check 0x8080 */
-       rtw89_phy_write32(rtwdev, 0x8000, 0x8);
+       rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
 
        ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
                                1000, false, rtwdev);

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 874cca85eaadf63366f7b23f9fb9fe39ae84c8eb..82af17d7d8d31ce3d417fef4444d71e6ed6f229e 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -4039,6 +4039,7 @@
 #define B_P0_RFM_TX_OPT BIT(6)
 #define B_P0_RFM_BT_EN BIT(5)
 #define B_P0_RFM_OUT GENMASK(4, 0)
+#define R_P0_PATH_RST 0x58AC
 #define R_P0_TXDPD 0x58D4
 #define B_P0_TXDPD GENMASK(31, 28)
 #define R_P0_TXPW_RSTB 0x58DC
@@ -4083,6 +4084,7 @@
 #define R_P1_RFCTM 0x7864
 #define R_P1_RFCTM_RDY BIT(26)
 #define B_P1_RFCTM_VAL GENMASK(25, 20)
+#define R_P1_PATH_RST 0x78AC
 #define R_P1_TXPW_RSTB 0x78DC
 #define B_P1_TXPW_RSTB_MANON BIT(30)
 #define B_P1_TXPW_RSTB_TSSI BIT(31)