RISC-V: Fix the typo in Scountovf CSR name

The counter overflow CSR name is "scountovf" not "sscountovf".

Fix the csr name.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-2-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 2468c55933cd0d5d55d71d83a52226172bd5121c..9d1b07932794e1cede7ce639426ef923ea03a59c 100644 (file)
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -281,7 +281,7 @@
 #define CSR_HPMCOUNTER30H      0xc9e
 #define CSR_HPMCOUNTER31H      0xc9f
 
-#define CSR_SSCOUNTOVF         0xda0
+#define CSR_SCOUNTOVF          0xda0
 
 #define CSR_SSTATUS            0x100
 #define CSR_SIE                        0x104

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 8cbe6e5f9c39a6f5b585251b02908b8b7309e23d..3e44d2fb8bf81d39f24f1af5b5a34a796d855f47 100644 (file)
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -27,7 +27,7 @@
 
 #define ALT_SBI_PMU_OVERFLOW(__ovl)                                    \
 asm volatile(ALTERNATIVE_2(                                            \
-       "csrr %0, " __stringify(CSR_SSCOUNTOVF),                        \
+       "csrr %0, " __stringify(CSR_SCOUNTOVF),                         \
        "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),             \
                THEAD_VENDOR_ID, ERRATA_THEAD_PMU,                      \
                CONFIG_ERRATA_THEAD_PMU,                                \