cxl/pci: Disable root port interrupts in RCH mode

The RCH root port contains root command AER registers that should not be
enabled.[1] Disable these to prevent root port interrupts.

[1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-17-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 3c85fd1ae5a99e888adcf216b2da0f2268299113..3da195caa4ad6155a7256bb701ab668b5fadd60b 100644 (file)
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -763,6 +763,35 @@ static void cxl_dport_map_regs(struct cxl_dport *dport)
                cxl_dport_map_rch_aer(dport);
 }
 
+static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
+{
+       void __iomem *aer_base = dport->regs.dport_aer;
+       struct pci_host_bridge *bridge;
+       u32 aer_cmd_mask, aer_cmd;
+
+       if (!aer_base)
+               return;
+
+       bridge = to_pci_host_bridge(dport->dport_dev);
+
+       /*
+        * Disable RCH root port command interrupts.
+        * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
+        *
+        * This sequence may not be necessary. CXL spec states disabling
+        * the root cmd register's interrupts is required. But, PCI spec
+        * shows these are disabled by default on reset.
+        */
+       if (bridge->native_cxl_error) {
+               aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
+                               PCI_ERR_ROOT_CMD_NONFATAL_EN |
+                               PCI_ERR_ROOT_CMD_FATAL_EN);
+               aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
+               aer_cmd &= ~aer_cmd_mask;
+               writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
+       }
+}
+
 void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
 {
        struct device *dport_dev = dport->dport_dev;
@@ -774,6 +803,9 @@ void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
 
        dport->reg_map.host = host;
        cxl_dport_map_regs(dport);
+
+       if (dport->rch)
+               cxl_disable_rch_root_ints(dport);
 }
 EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL);