mtd: spi-nor: Fix wrong TB selection of GD25Q256

For GD25Q256, wrong SR bit for top/bottom selection is being used.
Fix it to use appropriate bit.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 92b38157b38cd0718bbac7526a22b3730a97dd55..9ccde854f8ba991be6665534430fc26bf05cc236 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2395,7 +2395,8 @@ static const struct flash_info spi_nor_ids[] = {
        {
                "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
                        SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-                       SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+                       SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+                       SPI_NOR_TB_SR_BIT6)
                        .fixups = &gd25q256_fixups,
        },