drm/amd/display: Support vertical interrupt 0 for all dcn ASIC

[Why]
When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try
to register vertical interrupt 0 for specific task.

Currently, only dcn10 have defined relevant info for vertical interrupt
0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will
get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and
cause pointer errors.

[How]
Add support of vertical interrupt 0 for all dcn ASIC.

v2: squash in build fix (Alex)

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
index 3f1e7a196a23ab301bf7d3442ae1a730fc4fb340..c4b067d0189565f8801a8c3d35be2529fb07e9b0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -58,6 +58,18 @@ enum dc_irq_source to_dal_irq_source_dcn20(
                return DC_IRQ_SOURCE_VBLANK5;
        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK6;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
+       case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC3_VLINE0;
+       case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC4_VLINE0;
+       case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC5_VLINE0;
+       case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC6_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -172,6 +184,11 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
        .ack = NULL
 };
 
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -245,6 +262,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() \
        {\
                .funcs = &dummy_irq_info_funcs\
@@ -353,6 +378,12 @@ irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
        vblank_int_entry(3),
        vblank_int_entry(4),
        vblank_int_entry(5),
+       vline0_int_entry(0),
+       vline0_int_entry(1),
+       vline0_int_entry(2),
+       vline0_int_entry(3),
+       vline0_int_entry(4),
+       vline0_int_entry(5),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn20 = {

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
index 0e0f494fbb5e138b1f739cd664252d2899c2fc12..3908ad9291769cf04bf79f4d156105dbd38dfaa2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
@@ -58,6 +58,20 @@ enum dc_irq_source to_dal_irq_source_dcn21(
                return DC_IRQ_SOURCE_VBLANK5;
        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK6;
+       case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
+               return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
+       case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC3_VLINE0;
+       case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC4_VLINE0;
+       case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC5_VLINE0;
+       case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC6_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -173,6 +187,16 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
        .ack = NULL
 };
 
+static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 
@@ -254,6 +278,14 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() \
        {\
                .funcs = &dummy_irq_info_funcs\
@@ -366,6 +398,12 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
        vblank_int_entry(3),
        vblank_int_entry(4),
        vblank_int_entry(5),
+       vline0_int_entry(0),
+       vline0_int_entry(1),
+       vline0_int_entry(2),
+       vline0_int_entry(3),
+       vline0_int_entry(4),
+       vline0_int_entry(5),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn21 = {

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index a35b76772b9dfb5144b71655dc761687d7e945cd..4ec6f6ad8c4837765b0f9d84fb0bc72ef26214f0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -65,6 +65,20 @@ enum dc_irq_source to_dal_irq_source_dcn30(
                return DC_IRQ_SOURCE_VBLANK5;
        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK6;
+       case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
+               return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
+       case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC3_VLINE0;
+       case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC4_VLINE0;
+       case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC5_VLINE0;
+       case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC6_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -179,6 +193,16 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
        .ack = NULL
 };
 
+static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -252,6 +276,14 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() \
        {\
                .funcs = &dummy_irq_info_funcs\
@@ -360,6 +392,12 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
        vblank_int_entry(3),
        vblank_int_entry(4),
        vblank_int_entry(5),
+       vline0_int_entry(0),
+       vline0_int_entry(1),
+       vline0_int_entry(2),
+       vline0_int_entry(3),
+       vline0_int_entry(4),
+       vline0_int_entry(5),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn30 = {

diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
index 927fdc43fb9f0670809af2b06af4cfed61bdc228..2313a5664f44ba93230a35e28a8801aa784e7f8d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
@@ -50,6 +50,18 @@ static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_servi
                return DC_IRQ_SOURCE_VBLANK5;
        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
                return DC_IRQ_SOURCE_VBLANK6;
+       case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC1_VLINE0;
+       case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC2_VLINE0;
+       case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC3_VLINE0;
+       case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC4_VLINE0;
+       case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC5_VLINE0;
+       case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+               return DC_IRQ_SOURCE_DC6_VLINE0;
        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
                return DC_IRQ_SOURCE_PFLIP1;
        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
@@ -154,6 +166,11 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .ack = NULL
 };
 
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+       .set = NULL,
+       .ack = NULL
+};
+
 #undef BASE_INNER
 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 
@@ -222,6 +239,14 @@ static const struct irq_source_info_funcs vblank_irq_info_funcs = {
                .funcs = &vblank_irq_info_funcs\
        }
 
+#define vline0_int_entry(reg_num)\
+       [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+               IRQ_REG_ENTRY(OTG, reg_num,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+                       OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+               .funcs = &vline0_irq_info_funcs\
+       }
+
 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
 
 #define i2c_int_entry(reg_num) \
@@ -318,6 +343,11 @@ static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBE
                vblank_int_entry(2),
                vblank_int_entry(3),
                vblank_int_entry(4),
+               vline0_int_entry(0),
+               vline0_int_entry(1),
+               vline0_int_entry(2),
+               vline0_int_entry(3),
+               vline0_int_entry(4),
 };
 
 static const struct irq_service_funcs irq_service_funcs_dcn302 = {