LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE

LoongArch has hardware page coloring for L1 Cache, so we don't have
cache aliases. But SFB (Store Fill Buffer) still has aliases. So we
define SHMLBA to SZ_64K previously. But there are losts of applications
use PAGE_SIZE rather than SHMLBA to mmap() file pages and shared pages.
Of course we can fix them one by one, but not easy.

On the other hand, we can simply disable SFB for 4KB page size to fix
cache alias (there will be performance decrease, but acceptable), and
in future we will fix SFB in hardware. So we can safely define SHMLBA to
PAGE_SIZE (use the generic shmparam.h) to make life easier.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/include/asm/shmparam.h b/arch/loongarch/include/asm/shmparam.h
deleted file mode 100644 (file)
index c9554f4..0000000
--- a/arch/loongarch/include/asm/shmparam.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
- */
-#ifndef _ASM_SHMPARAM_H
-#define _ASM_SHMPARAM_H
-
-#define __ARCH_FORCE_SHMLBA    1
-
-#define        SHMLBA  SZ_64K           /* attach addr a multiple of this */
-
-#endif /* _ASM_SHMPARAM_H */

diff --git a/arch/loongarch/kernel/head.S b/arch/loongarch/kernel/head.S
index 53b883db0786207318b2cfc6857a05857b9dd1a9..be187e99d3587f50b2df56ae5b150085f7cfa095 100644 (file)
--- a/arch/loongarch/kernel/head.S
+++ b/arch/loongarch/kernel/head.S
@@ -75,6 +75,11 @@ SYM_CODE_START(kernel_entry)                 # kernel entry point
        la.pcrel        t0, fw_arg2
        st.d            a2, t0, 0
 
+#ifdef CONFIG_PAGE_SIZE_4KB
+       li.d            t0, 0
+       li.d            t1, CSR_STFILL
+       csrxchg         t0, t1, LOONGARCH_CSR_IMPCTL1
+#endif
        /* KSave3 used for percpu base, initialized as 0 */
        csrwr           zero, PERCPU_BASE_KS
        /* GPR21 used for percpu base (runtime), initialized as 0 */
@@ -127,6 +132,11 @@ SYM_CODE_START(smpboot_entry)
 
        JUMP_VIRT_ADDR  t0, t1
 
+#ifdef CONFIG_PAGE_SIZE_4KB
+       li.d            t0, 0
+       li.d            t1, CSR_STFILL
+       csrxchg         t0, t1, LOONGARCH_CSR_IMPCTL1
+#endif
        /* Enable PG */
        li.w            t0, 0xb0                # PLV=0, IE=0, PG=1
        csrwr           t0, LOONGARCH_CSR_CRMD