drm/i915/gen12: Invalidate aux table entries forcibly

Aux table invalidation can fail on update. So
next access may cause memory access to be into stale entry.

Proposed workaround is to invalidate entries between
all batchbuffers.

v2: correct register address (Yang)
v3: respect the order (Chris)

References bspec#43904, hsdes#1809175790
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chuansheng Liu <chuansheng.liu@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Yang A Shi <yang.a.shi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506165310.1239-1-mika.kuoppala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1235d5048372a72aeeb60e4c1f13cf4bf429943..bbdb0e2a45718e526ca500f1e96a634a853f56a3 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4539,6 +4539,17 @@ static u32 preparser_disable(bool state)
        return MI_ARB_CHECK | 1 << 8 | state;
 }
 
+static u32 *
+gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
+{
+       *cs++ = MI_LOAD_REGISTER_IMM(1);
+       *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
+       *cs++ = AUX_INV;
+       *cs++ = MI_NOOP;
+
+       return cs;
+}
+
 static int gen12_emit_flush_render(struct i915_request *request,
                                   u32 mode)
 {
@@ -4587,7 +4598,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
 
                flags |= PIPE_CONTROL_CS_STALL;
 
-               cs = intel_ring_begin(request, 8);
+               cs = intel_ring_begin(request, 8 + 4);
                if (IS_ERR(cs))
                        return PTR_ERR(cs);
 
@@ -4600,6 +4611,9 @@ static int gen12_emit_flush_render(struct i915_request *request,
 
                cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
 
+               /* hsdes: 1809175790 */
+               cs = gen12_emit_aux_table_inv(request, cs);
+
                *cs++ = preparser_disable(false);
                intel_ring_advance(request, cs);
        }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fde54b86ea207663bd748513c138d9bdc980f9cf..dc5952200a0733bbea8efdb9d9040ecce34ee113 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2557,6 +2557,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4)
 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
 #define BSD_HWS_PGA_GEN7       _MMIO(0x04180)
+#define GEN12_GFX_CCS_AUX_NV   _MMIO(0x4208)
+#define   AUX_INV              REG_BIT(0)
 #define BLT_HWS_PGA_GEN7       _MMIO(0x04280)
 #define VEBOX_HWS_PGA_GEN7     _MMIO(0x04380)
 #define RING_ACTHD(base)       _MMIO((base) + 0x74)