}
}
+void pmbus_idle(PMBusDevice *pmdev)
+{
+ pmdev->code = PMBUS_IDLE_STATE;
+}
+
/* assert the status_cml error upon receipt of malformed command */
static void pmbus_cml_error(PMBusDevice *pmdev)
{
}
break;
+ case PMBUS_IDLE_STATE:
+ pmbus_send8(pmdev, PMBUS_ERR_BYTE);
+ break;
+
case PMBUS_CLEAR_FAULTS: /* Send Byte */
case PMBUS_PAGE_PLUS_WRITE: /* Block Write-only */
case PMBUS_STORE_DEFAULT_ALL: /* Send Byte */
PMBUS_MFR_MAX_TEMP_1 = 0xC0, /* R/W word */
PMBUS_MFR_MAX_TEMP_2 = 0xC1, /* R/W word */
PMBUS_MFR_MAX_TEMP_3 = 0xC2, /* R/W word */
+ PMBUS_IDLE_STATE = 0xFF,
};
/* STATUS_WORD */
*/
void pmbus_check_limits(PMBusDevice *pmdev);
+/**
+ * Enter an idle state where only the PMBUS_ERR_BYTE will be returned
+ * indefinitely until a new command is issued.
+ */
+void pmbus_idle(PMBusDevice *pmdev);
+
extern const VMStateDescription vmstate_pmbus_device;
#define VMSTATE_PMBUS_DEVICE(_field, _state) { \