drm/amd/display: add seamless boot flag to stream

[Why]
If we determine the stream we are trying to commit
matches HW, we want to try to optimize.

[How]
Try to acquire the HW resources that are already enabled
and optimize.
Also skip backend reprogramming

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b620520771a7c4ddb161637da6a2cd24b2b8bacc..52f838442e21082ae1d0fa20beed15905b7414c9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1096,6 +1096,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                const struct dc_link *link = context->streams[i]->link;
                struct dc_stream_status *status;
 
+               if (context->streams[i]->apply_seamless_boot_optimization)
+                       context->streams[i]->apply_seamless_boot_optimization = false;
+
                if (!context->streams[i]->mode_changed)
                        continue;
 

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index e2e7bf2ba84b93916b700846e7ace531677e0f27..6d2cef05b4d7225ae1fedb9190944fd5a8c1b8dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2579,13 +2579,23 @@ void core_link_enable_stream(
                        &stream->timing);
 
        if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
+               bool apply_edp_fast_boot_optimization =
+                       pipe_ctx->stream->apply_edp_fast_boot_optimization;
+
+               pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+
                resource_build_info_frame(pipe_ctx);
                core_dc->hwss.update_info_frame(pipe_ctx);
 
+               /* Do not touch link on seamless boot optimization. */
+               if (pipe_ctx->stream->apply_seamless_boot_optimization) {
+                       pipe_ctx->stream->dpms_off = false;
+                       return;
+               }
+
                /* eDP lit up by bios already, no need to enable again. */
                if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
-                               pipe_ctx->stream->apply_edp_fast_boot_optimization) {
-                       pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+                                       apply_edp_fast_boot_optimization) {
                        pipe_ctx->stream->dpms_off = false;
                        return;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9888bc7659f32f1456fa538cd569887dfb872c36..349ab801777610f9070f3593e7010684203364db 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1800,6 +1800,51 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
                stream->phy_pix_clk *= 2;
 }
 
+static int acquire_resource_from_hw_enabled_state(
+               struct resource_context *res_ctx,
+               const struct resource_pool *pool,
+               struct dc_stream_state *stream)
+{
+       struct dc_link *link = stream->link;
+       unsigned int inst;
+
+       /* Check for enabled DIG to identify enabled display */
+       if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
+               return -1;
+
+       /* Check for which front end is used by this encoder.
+        * Note the inst is 1 indexed, where 0 is undefined.
+        * Note that DIG_FE can source from different OTG but our
+        * current implementation always map 1-to-1, so this code makes
+        * the same assumption and doesn't check OTG source.
+        */
+       inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
+
+       /* Instance should be within the range of the pool */
+       if (inst >= pool->pipe_count)
+               return -1;
+
+       if (!res_ctx->pipe_ctx[inst].stream) {
+               struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
+
+               pipe_ctx->stream_res.tg = pool->timing_generators[inst];
+               pipe_ctx->plane_res.mi = pool->mis[inst];
+               pipe_ctx->plane_res.hubp = pool->hubps[inst];
+               pipe_ctx->plane_res.ipp = pool->ipps[inst];
+               pipe_ctx->plane_res.xfm = pool->transforms[inst];
+               pipe_ctx->plane_res.dpp = pool->dpps[inst];
+               pipe_ctx->stream_res.opp = pool->opps[inst];
+               if (pool->dpps[inst])
+                       pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
+               pipe_ctx->pipe_idx = inst;
+
+               pipe_ctx->stream = stream;
+               return inst;
+       }
+
+       return -1;
+}
+
 enum dc_status resource_map_pool_resources(
                const struct dc  *dc,
                struct dc_state *context,
@@ -1824,8 +1869,15 @@ enum dc_status resource_map_pool_resources(
 
        calculate_phy_pix_clks(stream);
 
-       /* acquire new resources */
-       pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
+       if (stream->apply_seamless_boot_optimization)
+               pipe_idx = acquire_resource_from_hw_enabled_state(
+                               &context->res_ctx,
+                               pool,
+                               stream);
+
+       if (pipe_idx < 0)
+               /* acquire new resources */
+               pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
 
 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
        if (pipe_idx < 0)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 90f019eb54b35574031434f877b77bf60b265d47..a798694992b9eb73168f0f5cfbca47203ec9be0a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -119,7 +119,6 @@ struct dc_stream_state {
        int phy_pix_clk;
        enum signal_type signal;
        bool dpms_off;
-       bool apply_edp_fast_boot_optimization;
 
        void *dm_stream_context;
 
@@ -146,6 +145,9 @@ struct dc_stream_state {
                uint8_t otg_offset;
        } out;
 
+       bool apply_edp_fast_boot_optimization;
+       bool apply_seamless_boot_optimization;
+
        uint32_t stream_id;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e2d8362dd5b16b9ec2d703a4aaf6fd8fa733ddaf..21ceda410244f1f796b45104a3b25f1e6cb19429 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1339,7 +1339,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(
        }
 
        /*  */
-       dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
+       /* Do not touch stream timing on seamless boot optimization. */
+       if (!pipe_ctx->stream->apply_seamless_boot_optimization)
+               dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
 
        if (pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt)
                pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt(