#define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
 #define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
 #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
+#define ISC_PFE_CFG0_CCIR656    BIT(9)
+#define ISC_PFE_CFG0_CCIR_CRC   BIT(10)
 
 #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
 #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
 
        pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
        mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
               ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
-              ISC_PFE_CFG0_MODE_MASK;
+              ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
+                  ISC_PFE_CFG0_CCIR656;
 
        regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 
                if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
                        subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;
 
+               if (v4l2_epn.bus_type == V4L2_MBUS_BT656)
+                       subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |
+                                       ISC_PFE_CFG0_CCIR656;
+
                subdev_entity->asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
                subdev_entity->asd->match.fwnode =
                        of_fwnode_handle(rem);