arm: perf: Convert remaining fields to use GENMASK

Convert the remaining fields to use either GENMASK or be built from
other fields. These all already started at bit 0 so don't need a code
change for the lack of _SHIFT.

Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20231211161331.1277825-5-james.clark@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
index 36bc00494f56c7f2f7f83ff9613079770eaec5e1..a93b4cf885624047544475f0adc96546a1a4984d 100644 (file)
--- a/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@ -675,7 +675,7 @@ static u32 armv8pmu_getreset_flags(void)
        value = read_pmovsclr();
 
        /* Write to clear flags */
-       value &= ARMV8_PMU_OVSR_MASK;
+       value &= ARMV8_PMU_OVERFLOWED_MASK;
        write_pmovsclr(value);
 
        return value;

diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h
index 1bc7678c10d4f3d0548437fe1d969efb85696ddd..daa63542242dde9281247574db23c816e57ded4e 100644 (file)
--- a/include/linux/perf/arm_pmuv3.h
+++ b/include/linux/perf/arm_pmuv3.h
@@ -216,19 +216,25 @@
 #define ARMV8_PMU_PMCR_LC      (1 << 6) /* Overflow on 64 bit cycle counter */
 #define ARMV8_PMU_PMCR_LP      (1 << 7) /* Long event counter enable */
 #define ARMV8_PMU_PMCR_N       GENMASK(15, 11) /* Number of counters supported */
-#define ARMV8_PMU_PMCR_MASK    0xff    /* Mask for writable bits */
+/* Mask for writable bits */
+#define ARMV8_PMU_PMCR_MASK    (ARMV8_PMU_PMCR_E | ARMV8_PMU_PMCR_P | \
+                                ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_D | \
+                                ARMV8_PMU_PMCR_X | ARMV8_PMU_PMCR_DP | \
+                                ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)
 
 /*
  * PMOVSR: counters overflow flag status reg
  */
-#define ARMV8_PMU_OVSR_MASK            0xffffffff      /* Mask for writable bits */
-#define ARMV8_PMU_OVERFLOWED_MASK      ARMV8_PMU_OVSR_MASK
+#define ARMV8_PMU_OVSR_P               GENMASK(30, 0)
+#define ARMV8_PMU_OVSR_C               BIT(31)
+/* Mask for writable bits is both P and C fields */
+#define ARMV8_PMU_OVERFLOWED_MASK      (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C)
 
 /*
  * PMXEVTYPER: Event selection reg
  */
 #define ARMV8_PMU_EVTYPE_MASK  0xc800ffff      /* Mask for writable bits */
-#define ARMV8_PMU_EVTYPE_EVENT 0xffff          /* Mask for EVENT bits */
+#define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0)  /* Mask for EVENT bits */
 
 /*
  * Event filters for PMUv3
@@ -243,11 +249,13 @@
 /*
  * PMUSERENR: user enable reg
  */
-#define ARMV8_PMU_USERENR_MASK 0xf             /* Mask for writable bits */
 #define ARMV8_PMU_USERENR_EN   (1 << 0) /* PMU regs can be accessed at EL0 */
 #define ARMV8_PMU_USERENR_SW   (1 << 1) /* PMSWINC can be written at EL0 */
 #define ARMV8_PMU_USERENR_CR   (1 << 2) /* Cycle counter can be read at EL0 */
 #define ARMV8_PMU_USERENR_ER   (1 << 3) /* Event counter can be read at EL0 */
+/* Mask for writable bits */
+#define ARMV8_PMU_USERENR_MASK (ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \
+                                ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER)
 
 /* PMMIR_EL1.SLOTS mask */
 #define ARMV8_PMU_SLOTS                GENMASK(7, 0)