PCI/ATS: Show PASID Capability register width in bitmasks

The PASID Capability and Control registers are both 16 bits wide.  Use
16-bit wide constants in field names to match the register width.  No
functional change intended.

Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 0fd621505246b17f1279b047c357ddbc5049e5bb..f35d73efe223796f418946c94787c6f36814ab93 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -930,12 +930,12 @@
 
 /* Process Address Space ID */
 #define PCI_PASID_CAP          0x04    /* PASID feature register */
-#define  PCI_PASID_CAP_EXEC    0x02    /* Exec permissions Supported */
-#define  PCI_PASID_CAP_PRIV    0x04    /* Privilege Mode Supported */
+#define  PCI_PASID_CAP_EXEC    0x0002  /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV    0x0004  /* Privilege Mode Supported */
 #define PCI_PASID_CTRL         0x06    /* PASID control register */
-#define  PCI_PASID_CTRL_ENABLE 0x01    /* Enable bit */
-#define  PCI_PASID_CTRL_EXEC   0x02    /* Exec permissions Enable */
-#define  PCI_PASID_CTRL_PRIV   0x04    /* Privilege Mode Enable */
+#define  PCI_PASID_CTRL_ENABLE 0x0001  /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC   0x0002  /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV   0x0004  /* Privilege Mode Enable */
 #define PCI_EXT_CAP_PASID_SIZEOF       8
 
 /* Single Root I/O Virtualization */