mmc: sdhci_am654: Fix ITAPDLY for HS400 timing

While STRB is currently used for DATA and CRC responses, the CMD
responses from the device to the host still require ITAPDLY for
HS400 timing.

Currently what is stored for HS400 is the ITAPDLY from High Speed
mode which is incorrect. The ITAPDLY for HS400 speed mode should
be the same as ITAPDLY as HS200 timing after tuning is executed.
Add the functionality to save ITAPDLY from HS200 tuning and save
as HS400 ITAPDLY.

Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes")
Signed-off-by: Judith Mendez <jm@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20240320223837.959900-8-jm@ti.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 884d1b53180d7c47b24c76d3267d6dfe8fcc1fef..562034af653ebbff3ab8347a28a8f8e83930e8c4 100644 (file)
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -301,6 +301,12 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
        if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
                sdhci_am654_setup_dll(host, clock);
                sdhci_am654->dll_enable = true;
+
+               if (timing == MMC_TIMING_MMC_HS400) {
+                       sdhci_am654->itap_del_ena[timing] = 0x1;
+                       sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
+               }
+
                sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
                                          sdhci_am654->itap_del_ena[timing]);
        } else {
@@ -531,6 +537,9 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
 
        sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
 
+       /* Save ITAPDLY */
+       sdhci_am654->itap_del_sel[timing] = itap;
+
        return 0;
 }