ARM: dts: imx7[d]-mba7: Move ethernet PHY reset into PHY node

Split pinctrl as well. 'reset-deassert-us' is added with a small safe
margin.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
index 2e406cc7d292aac565a23671af406ddafe34af48..c2be1a75f70df71d3bf638a5f05d6cee58826544 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
@@ -214,8 +214,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
        phy-mode = "rgmii-id";
-       phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
-       phy-reset-duration = <1>;
        phy-supply = <&reg_fec1_pwdn>;
        phy-handle = <&ethphy1_0>;
        fsl,magic-packet;
@@ -228,10 +226,15 @@
                ethphy1_0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_enet1_phy>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                        ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+                       reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <1000>;
+                       reset-deassert-us = <500>;
                };
        };
 };
@@ -366,7 +369,11 @@
                        <MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1              0x79>,
                        <MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2              0x79>,
                        <MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3              0x79>,
-                       <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL        0x79>,
+                       <MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL        0x79>;
+       };
+
+       pinctrl_enet1_phy: enet1phygrp {
+               fsl,pins =
                        /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
                        <MX7D_PAD_ENET1_COL__GPIO7_IO15                         0x40000070>,
                        /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */

diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts
index 79a6d82b453aaed46c0c3544c37010b085601b89..4ea1801a7aed313eaaea0b853101615009b98d1d 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts
@@ -21,8 +21,6 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2>;
        phy-mode = "rgmii-id";
-       phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
-       phy-reset-duration = <1>;
        phy-supply = <&reg_fec2_pwdn>;
        phy-handle = <&ethphy2_0>;
        fsl,magic-packet;
@@ -35,10 +33,15 @@
                ethphy2_0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_enet2_phy>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                        ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+                       reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <1000>;
+                       reset-deassert-us = <500>;
                };
        };
 };
@@ -62,7 +65,11 @@
                        <MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1            0x79>,
                        <MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2            0x79>,
                        <MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3           0x79>,
-                       <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL        0x79>,
+                       <MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL        0x79>;
+       };
+
+       pinctrl_enet2_phy: enet2phygrp {
+               fsl,pins =
                        /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
                        <MX7D_PAD_EPDC_BDR0__GPIO2_IO28         0x40000070>,
                        /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */