phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
new file mode 100644 (file)
index 0000000..86d7d79
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
+#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
+
+#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL                     0xa0
+#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES                       0xb0
+#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1                     0xb4
+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1               0xc4
+#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2               0xc8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0                 0xd4
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1                 0xd8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2                 0xdc
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3                 0xe0
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4                 0xe4
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5                 0xe8
+#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6                 0xec
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210      0xf0
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3                0xf4
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210      0xf8
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3                0xfc
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210      0x100
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3                0x104
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3                0x10c
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3                0x114
+#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3                0x11c
+#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE              0x128
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index e5974e6caf51f46c7fb7ed51e84038cdb009b262..148663ee713af7ba4d7dcd7258122a9f09cbbd51 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -24,6 +24,7 @@
 #include "phy-qcom-qmp-qserdes-com-v6.h"
 #include "phy-qcom-qmp-qserdes-txrx-v6.h"
 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
+#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
 
 #include "phy-qcom-qmp-qserdes-pll.h"