drm/dp_mst: Fix PBN divider calculation for UHBR rates

The current way of calculating the pbn_div value, the link BW per each
MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR
rates calculating with the correct channel coding efficiency based on
the link rate.

v2:
- Return the fractional pbn_div value from drm_dp_get_vc_payload_bw().
v3:
- Fix rounding up quotient while calculating req_slots. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231117150929.1767227-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7efbd8ef664f06071c40d8d2a004ea3d8198e5e4..ab39c7ad9b899007128c9dd4da893e468cdbb98c 100644 (file)
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3585,14 +3585,18 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
 fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
                                    int link_rate, int link_lane_count)
 {
+       int ch_coding_efficiency =
+               drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate));
        fixed20_12 ret;
 
        if (link_rate == 0 || link_lane_count == 0)
                drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
                            link_rate, link_lane_count);
 
-       /* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
-       ret.full = dfixed_const(link_rate * link_lane_count / 54000);
+       /* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
+       ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,
+                                                 ch_coding_efficiency),
+                                     (1000000ULL * 8 * 5400) >> 12);
 
        return ret;
 }
@@ -4342,7 +4346,7 @@ int drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
                }
        }
 
-       req_slots = DIV_ROUND_UP(pbn, dfixed_trunc(topology_state->pbn_div));
+       req_slots = DIV_ROUND_UP(dfixed_const(pbn), topology_state->pbn_div.full);
 
        drm_dbg_atomic(mgr->dev, "[CONNECTOR:%d:%s] [MST PORT:%p] TU %d -> %d\n",
                       port->connector->base.id, port->connector->name,

diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 194715083399ef11f254b89de7165a4cf8f8d471..b88cc53425e0be1c9085d2dc09a1201419e951c1 100644 (file)
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -252,6 +252,19 @@ drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
        return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
 }
 
+/**
+ * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
+ * @link_rate: link rate in 10kbits/s units
+ *
+ * Determine if the provided link rate is an UHBR rate.
+ *
+ * Returns: %True if @link_rate is an UHBR rate.
+ */
+static inline bool drm_dp_is_uhbr_rate(int link_rate)
+{
+       return link_rate >= 1000000;
+}
+
 /*
  * DisplayPort AUX channel
  */