powerpc/bpf: Only pad length-variable code at initial pass

Now that two real additional passes are performed in case of extra pass
requested by BPF core, padding is not needed anymore except during
initial pass done before memory allocation to count maximum possible
program size.

So, only do the padding when 'image' is NULL.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/921851d6577badc1e6b08b270a0ced80a6a26d03.1675245773.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/net/bpf_jit_comp32.c b/arch/powerpc/net/bpf_jit_comp32.c
index 20493b85124814d2c73f2038bc361d83ddb80f2a..c3bc20b91cdc0621ed1273e0f7606ce1a5bcb95f 100644 (file)
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -206,9 +206,6 @@ int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func
 
        if (image && rel < 0x2000000 && rel >= -0x2000000) {
                PPC_BL(func);
-               EMIT(PPC_RAW_NOP());
-               EMIT(PPC_RAW_NOP());
-               EMIT(PPC_RAW_NOP());
        } else {
                /* Load function address into r0 */
                EMIT(PPC_RAW_LIS(_R0, IMM_H(func)));
@@ -973,8 +970,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *
                        PPC_LI32(dst_reg_h, (u32)insn[i + 1].imm);
                        PPC_LI32(dst_reg, (u32)insn[i].imm);
                        /* padding to allow full 4 instructions for later patching */
-                       for (j = ctx->idx - tmp_idx; j < 4; j++)
-                               EMIT(PPC_RAW_NOP());
+                       if (!image)
+                               for (j = ctx->idx - tmp_idx; j < 4; j++)
+                                       EMIT(PPC_RAW_NOP());
                        /* Adjust for two bpf instructions */
                        addrs[++i] = ctx->idx * 4;
                        break;

diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c
index 6298c1483081ab4a5a0bf14ca4966392966724dd..8dd3cabaa83ad3ff04e4cdae25b79761fb7e0298 100644 (file)
--- a/arch/powerpc/net/bpf_jit_comp64.c
+++ b/arch/powerpc/net/bpf_jit_comp64.c
@@ -240,13 +240,14 @@ int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func
         * load the callee's address, but this may optimize the number of
         * instructions required based on the nature of the address.
         *
-        * Since we don't want the number of instructions emitted to change,
+        * Since we don't want the number of instructions emitted to increase,
         * we pad the optimized PPC_LI64() call with NOPs to guarantee that
         * we always have a five-instruction sequence, which is the maximum
         * that PPC_LI64() can emit.
         */
-       for (i = ctx->idx - ctx_idx; i < 5; i++)
-               EMIT(PPC_RAW_NOP());
+       if (!image)
+               for (i = ctx->idx - ctx_idx; i < 5; i++)
+                       EMIT(PPC_RAW_NOP());
 
        EMIT(PPC_RAW_MTCTR(_R12));
        EMIT(PPC_RAW_BCTRL());
@@ -938,8 +939,9 @@ emit_clear:
                        tmp_idx = ctx->idx;
                        PPC_LI64(dst_reg, imm64);
                        /* padding to allow full 5 instructions for later patching */
-                       for (j = ctx->idx - tmp_idx; j < 5; j++)
-                               EMIT(PPC_RAW_NOP());
+                       if (!image)
+                               for (j = ctx->idx - tmp_idx; j < 5; j++)
+                                       EMIT(PPC_RAW_NOP());
                        /* Adjust for two bpf instructions */
                        addrs[++i] = ctx->idx * 4;
                        break;