drm/msm/dpu: Print interrupt index in addition to the mask

The mask only describes the `irq_idx % 32` part, making it generally
impossible to deduce what interrupt is being enabled/disabled.  Since
`debug/core_irq` in debugfs (and other prints) also include the full
`DPU_IRQ_IDX()` value, print the same full value here for easier
correlation instead of only adding the `irq_idx / 32` part.

Furthermore, make the dbgstr messages more consistent.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/512460/
Link: https://lore.kernel.org/r/20221121222456.437815-1-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index cf1b6d84c18a3c750710263005d08ff8ee0212f9..64589a9c2c519f30e53a075adf634a2a89ca1707 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -252,9 +252,9 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
 
        cache_irq_mask = intr->cache_irq_mask[reg_idx];
        if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
-               dbgstr = "DPU IRQ already set:";
+               dbgstr = "already ";
        } else {
-               dbgstr = "DPU IRQ enabled:";
+               dbgstr = "";
 
                cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
                /* Cleaning any pending interrupt */
@@ -268,7 +268,7 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
                intr->cache_irq_mask[reg_idx] = cache_irq_mask;
        }
 
-       pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
+       pr_debug("DPU IRQ %d %senabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", irq_idx, dbgstr,
                        DPU_IRQ_MASK(irq_idx), cache_irq_mask);
 
        return 0;
@@ -301,9 +301,9 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
 
        cache_irq_mask = intr->cache_irq_mask[reg_idx];
        if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
-               dbgstr = "DPU IRQ is already cleared:";
+               dbgstr = "already ";
        } else {
-               dbgstr = "DPU IRQ mask disable:";
+               dbgstr = "";
 
                cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
                /* Disable interrupts based on the new mask */
@@ -317,7 +317,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
                intr->cache_irq_mask[reg_idx] = cache_irq_mask;
        }
 
-       pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
+       pr_debug("DPU IRQ %d %sdisabled: MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", irq_idx, dbgstr,
                        DPU_IRQ_MASK(irq_idx), cache_irq_mask);
 
        return 0;