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target/ppc: Fix xxbrq, xxbrw
author
Anton Blanchard
<anton@ozlabs.org>
Tue, 7 May 2019 00:48:05 +0000
(10:48 +1000)
committer
David Gibson
<david@gibson.dropbear.id.au>
Wed, 29 May 2019 01:39:44 +0000
(11:39 +1000)
Fix a typo in xxbrq and xxbrw where we put both results into the lower
doubleword.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access")
Signed-off-by: Anton Blanchard <anton@ozlabs.org>
Message-Id: <
20190507004811
.29968-3-anton@ozlabs.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target/ppc/translate/vsx-impl.inc.c
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diff --git
a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 4d8ca7cf321a930043831194b533275b2b0ac21a..d29f60e2f91ada0b535410ce634584bb7170a882 100644
(file)
--- a/
target/ppc/translate/vsx-impl.inc.c
+++ b/
target/ppc/translate/vsx-impl.inc.c
@@
-1192,7
+1192,7
@@
static void gen_xxbrq(DisasContext *ctx)
tcg_gen_bswap64_i64(xtl, xbh);
set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_gen_mov_i64(xth, t0);
- set_cpu_vsr
l
(xT(ctx->opcode), xth);
+ set_cpu_vsr
h
(xT(ctx->opcode), xth);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(xth);
@@
-1220,7
+1220,7
@@
static void gen_xxbrw(DisasContext *ctx)
get_cpu_vsrl(xbl, xB(ctx->opcode));
gen_bswap32x4(xth, xtl, xbh, xbl);
- set_cpu_vsr
l
(xT(ctx->opcode), xth);
+ set_cpu_vsr
h
(xT(ctx->opcode), xth);
set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_temp_free_i64(xth);