drm/amd/display: Fix dpp dto for disabled pipes

[Why]
When switching from 1 pipe to 4to1 mpc combine,
DppDtoClk aren't enabled for the disabled pipes
pior to programming the pipes. Upon optimizing
bandwidth, DppDto are enabled causing intermittent
underflow.

[How]
Update dppclk dto whenever pipe are flagged to
enable.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index aed8ab06b41d3d1532da12792747461725e8232e..facd4e01b7ac126a8770140e69e2378ff840cd5d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1436,11 +1436,15 @@ static void dcn20_update_dchubp_dpp(
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct dpp *dpp = pipe_ctx->plane_res.dpp;
        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+       struct dccg *dccg = dc->res_pool->dccg;
        bool viewport_changed = false;
 
        if (pipe_ctx->update_flags.bits.dppclk)
                dpp->funcs->dpp_dppclk_control(dpp, false, true);
 
+       if (pipe_ctx->update_flags.bits.enable)
+               dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
+
        /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
         * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
         * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG