drm/rockchip: vop: Add NV15, NV20 and NV30 support

Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
Also add support for 10-bit 4:4:4 format while at it.

V5: Use drm_format_info_min_pitch() for correct bpp
    Add missing NV21, NV61 and NV42 formats
V4: Rework RK3328/RK3399 win0/1 data to not affect RK3368
V2: Added NV30 support

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jonas@kwiboo.se

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index e1ea50c8fd395432f58ee12929a6572df3fb4496..066299894d0480bc4ec7c6aac371c3d3e9bd1c9c 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -272,6 +272,18 @@ static bool has_uv_swapped(uint32_t format)
        }
 }
 
+static bool is_fmt_10(uint32_t format)
+{
+       switch (format) {
+       case DRM_FORMAT_NV15:
+       case DRM_FORMAT_NV20:
+       case DRM_FORMAT_NV30:
+               return true;
+       default:
+               return false;
+       }
+}
+
 static enum vop_data_format vop_convert_format(uint32_t format)
 {
        switch (format) {
@@ -287,12 +299,15 @@ static enum vop_data_format vop_convert_format(uint32_t format)
        case DRM_FORMAT_BGR565:
                return VOP_FMT_RGB565;
        case DRM_FORMAT_NV12:
+       case DRM_FORMAT_NV15:
        case DRM_FORMAT_NV21:
                return VOP_FMT_YUV420SP;
        case DRM_FORMAT_NV16:
+       case DRM_FORMAT_NV20:
        case DRM_FORMAT_NV61:
                return VOP_FMT_YUV422SP;
        case DRM_FORMAT_NV24:
+       case DRM_FORMAT_NV30:
        case DRM_FORMAT_NV42:
                return VOP_FMT_YUV444SP;
        default:
@@ -939,7 +954,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
        dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
        dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 
-       offset = (src->x1 >> 16) * fb->format->cpp[0];
+       if (fb->format->char_per_block[0])
+               offset = drm_format_info_min_pitch(fb->format, 0,
+                                                  src->x1 >> 16);
+       else
+               offset = (src->x1 >> 16) * fb->format->cpp[0];
+
        offset += (src->y1 >> 16) * fb->pitches[0];
        dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 
@@ -965,6 +985,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
        }
 
        VOP_WIN_SET(vop, win, format, format);
+       VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
        VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
        VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
        VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
@@ -974,15 +995,16 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
                    (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 
        if (is_yuv) {
-               int hsub = fb->format->hsub;
-               int vsub = fb->format->vsub;
-               int bpp = fb->format->cpp[1];
-
                uv_obj = fb->obj[1];
                rk_uv_obj = to_rockchip_obj(uv_obj);
 
-               offset = (src->x1 >> 16) * bpp / hsub;
-               offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
+               if (fb->format->char_per_block[1])
+                       offset = drm_format_info_min_pitch(fb->format, 1,
+                                                          src->x1 >> 16);
+               else
+                       offset = (src->x1 >> 16) * fb->format->cpp[1];
+               offset /= fb->format->hsub;
+               offset += (src->y1 >> 16) * fb->pitches[1] / fb->format->vsub;
 
                dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
                VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 5f56e0597df84a9f2a00ba63e6ab127a5b03cde9..4b2daefeb8c14e1f6fd8b518d3a1f4638e860b94 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -186,6 +186,7 @@ struct vop_win_phy {
        struct vop_reg enable;
        struct vop_reg gate;
        struct vop_reg format;
+       struct vop_reg fmt_10;
        struct vop_reg rb_swap;
        struct vop_reg uv_swap;
        struct vop_reg act_info;

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index d053ef0275526ec19502386b1828f0d087c957d6..c51ca82320cb0c09d2fea4909ea560b706ec191b 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] = {
        DRM_FORMAT_NV42,
 };
 
+static const uint32_t formats_win_full_10[] = {
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_RGB888,
+       DRM_FORMAT_BGR888,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_BGR565,
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_NV21,
+       DRM_FORMAT_NV16,
+       DRM_FORMAT_NV61,
+       DRM_FORMAT_NV24,
+       DRM_FORMAT_NV42,
+       DRM_FORMAT_NV15,
+       DRM_FORMAT_NV20,
+       DRM_FORMAT_NV30,
+};
+
 static const uint64_t format_modifiers_win_full[] = {
        DRM_FORMAT_MOD_LINEAR,
        DRM_FORMAT_MOD_INVALID,
@@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
 
 static const struct vop_win_phy rk3288_win01_data = {
        .scl = &rk3288_win_full_scl,
-       .data_formats = formats_win_full,
-       .nformats = ARRAY_SIZE(formats_win_full),
+       .data_formats = formats_win_full_10,
+       .nformats = ARRAY_SIZE(formats_win_full_10),
        .format_modifiers = format_modifiers_win_full,
        .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
        .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+       .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
        .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
        .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
        .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
@@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
 
 };
 
-static const struct vop_win_phy rk3399_win01_data = {
+static const struct vop_win_phy rk3399_win0_data = {
        .scl = &rk3288_win_full_scl,
-       .data_formats = formats_win_full,
-       .nformats = ARRAY_SIZE(formats_win_full),
+       .data_formats = formats_win_full_10,
+       .nformats = ARRAY_SIZE(formats_win_full_10),
        .format_modifiers = format_modifiers_win_full_afbc,
        .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
        .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+       .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
+       .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
+       .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
+       .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
+       .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
+       .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
+       .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
+       .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
+       .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
+       .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
+       .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
+       .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
+       .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
+       .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+       .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
+};
+
+static const struct vop_win_phy rk3399_win1_data = {
+       .scl = &rk3288_win_full_scl,
+       .data_formats = formats_win_full_10,
+       .nformats = ARRAY_SIZE(formats_win_full_10),
+       .format_modifiers = format_modifiers_win_full,
+       .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
+       .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+       .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
        .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
        .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
        .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
@@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data = {
  * AFBC on the primary plane.
  */
 static const struct vop_win_data rk3399_vop_win_data[] = {
-       { .base = 0x00, .phy = &rk3399_win01_data,
+       { .base = 0x00, .phy = &rk3399_win0_data,
          .type = DRM_PLANE_TYPE_PRIMARY },
-       { .base = 0x40, .phy = &rk3368_win01_data,
+       { .base = 0x40, .phy = &rk3399_win1_data,
          .type = DRM_PLANE_TYPE_OVERLAY },
        { .base = 0x00, .phy = &rk3368_win23_data,
          .type = DRM_PLANE_TYPE_OVERLAY },
@@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr = {
 };
 
 static const struct vop_win_data rk3328_vop_win_data[] = {
-       { .base = 0xd0, .phy = &rk3368_win01_data,
+       { .base = 0xd0, .phy = &rk3399_win1_data,
          .type = DRM_PLANE_TYPE_PRIMARY },
-       { .base = 0x1d0, .phy = &rk3368_win01_data,
+       { .base = 0x1d0, .phy = &rk3399_win1_data,
          .type = DRM_PLANE_TYPE_OVERLAY },
-       { .base = 0x2d0, .phy = &rk3368_win01_data,
+       { .base = 0x2d0, .phy = &rk3399_win1_data,
          .type = DRM_PLANE_TYPE_CURSOR },
 };