wifi: rtw89: phy: set TX power by rate according to chip gen

Wi-Fi 6 chips and Wi-Fi 7 chips have different register design for
TX power by rate. We rename original setting stuffs with a suffix
`_ax` and implement setting flow for Wi-Fi 7 chips. Then, we set TX
power by rate according to chip generation.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231003015446.14658-3-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c
index 05b0ca3d75fe73e530c659e0a5f842fc17020cae..02056936dc7c140af59f467925d92df31f1be1be 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.c
+++ b/drivers/net/wireless/realtek/rtw89/phy.c
@@ -1519,7 +1519,7 @@ void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
 }
 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
 
-static const u8 rtw89_rs_idx_num[] = {
+static const u8 rtw89_rs_idx_num_ax[] = {
        [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
        [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
        [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
@@ -1527,7 +1527,7 @@ static const u8 rtw89_rs_idx_num[] = {
        [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
 };
 
-static const u8 rtw89_rs_nss_num[] = {
+static const u8 rtw89_rs_nss_num_ax[] = {
        [RTW89_RS_CCK] = 1,
        [RTW89_RS_OFDM] = 1,
        [RTW89_RS_MCS] = RTW89_NSS_NUM,
@@ -1589,7 +1589,6 @@ static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
        return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
 }
 
-static
 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
                               const struct rtw89_rate_desc *rate_desc)
 {
@@ -2098,9 +2097,9 @@ void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
        }
 }
 
-void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
-                               const struct rtw89_chan *chan,
-                               enum rtw89_phy_idx phy_idx)
+static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
+                                         const struct rtw89_chan *chan,
+                                         enum rtw89_phy_idx phy_idx)
 {
        u8 max_nss_num = rtwdev->chip->rf_path_num;
        static const u8 rs[] = {
@@ -2119,19 +2118,19 @@ void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
        rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
                    "[TXPWR] set txpwr byrate with ch=%d\n", ch);
 
-       BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_CCK] % 4);
-       BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_OFDM] % 4);
-       BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_MCS] % 4);
-       BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_HEDCM] % 4);
+       BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
+       BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
+       BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
+       BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
 
        addr = R_AX_PWR_BY_RATE;
        for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
                for (i = 0; i < ARRAY_SIZE(rs); i++) {
-                       if (cur.nss >= rtw89_rs_nss_num[rs[i]])
+                       if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
                                continue;
 
                        cur.rs = rs[i];
-                       for (cur.idx = 0; cur.idx < rtw89_rs_idx_num[rs[i]];
+                       for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
                             cur.idx++) {
                                v[cur.idx % 4] =
                                        rtw89_phy_read_txpwr_byrate(rtwdev,
@@ -2153,7 +2152,6 @@ void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
                }
        }
 }
-EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate);
 
 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
                                const struct rtw89_chan *chan,
@@ -4905,5 +4903,7 @@ const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
        .cr_base = 0x10000,
        .ccx = &rtw89_ccx_regs_ax,
        .physts = &rtw89_physts_regs_ax,
+
+       .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
 };
 EXPORT_SYMBOL(rtw89_phy_gen_ax);

diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h
index 4684feac97b2b850c535bc229b657d4e7722cc55..78beafda3726626bd0a0e78c852e6cd1b4325b44 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy.h
+++ b/drivers/net/wireless/realtek/rtw89/phy.h
@@ -404,6 +404,10 @@ struct rtw89_phy_gen_def {
        u32 cr_base;
        const struct rtw89_ccx_regs *ccx;
        const struct rtw89_physts_regs *physts;
+
+       void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
+                                const struct rtw89_chan *chan,
+                                enum rtw89_phy_idx phy_idx);
 };
 
 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
@@ -616,13 +620,23 @@ u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
                           struct rtw89_txpwr_byrate *head,
                           const struct rtw89_rate_desc *desc);
+s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
+                              const struct rtw89_rate_desc *rate_desc);
 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
                                 const struct rtw89_txpwr_table *tbl);
 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
                              u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
+
+static inline
 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
                                const struct rtw89_chan *chan,
-                               enum rtw89_phy_idx phy_idx);
+                               enum rtw89_phy_idx phy_idx)
+{
+       const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+
+       phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
+}
+
 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
                                const struct rtw89_chan *chan,
                                enum rtw89_phy_idx phy_idx);

diff --git a/drivers/net/wireless/realtek/rtw89/phy_be.c b/drivers/net/wireless/realtek/rtw89/phy_be.c
index 778e4b0c8e8718bc2183d2ddca39df4a26239277..7b43bcd0952c8f85766d1f0f490438895af5ddb9 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/phy_be.c
+++ b/drivers/net/wireless/realtek/rtw89/phy_be.c
@@ -2,6 +2,8 @@
 /* Copyright(c) 2023  Realtek Corporation
  */
 
+#include "debug.h"
+#include "mac.h"
 #include "phy.h"
 #include "reg.h"
 
@@ -69,9 +71,114 @@ static const struct rtw89_physts_regs rtw89_physts_regs_be = {
        .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
 };
 
+struct rtw89_byr_spec_ent_be {
+       struct rtw89_rate_desc init;
+       u8 num_of_idx;
+       bool no_over_bw40;
+       bool no_multi_nss;
+};
+
+static const struct rtw89_byr_spec_ent_be rtw89_byr_spec_be[] = {
+       {
+               .init = { .rs = RTW89_RS_CCK },
+               .num_of_idx = RTW89_RATE_CCK_NUM,
+               .no_over_bw40 = true,
+               .no_multi_nss = true,
+       },
+       {
+               .init = { .rs = RTW89_RS_OFDM },
+               .num_of_idx = RTW89_RATE_OFDM_NUM,
+               .no_multi_nss = true,
+       },
+       {
+               .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_NON_OFDMA },
+               .num_of_idx = 2,
+               .no_multi_nss = true,
+       },
+       {
+               .init = { .rs = RTW89_RS_MCS, .idx = 14, .ofdma = RTW89_OFDMA },
+               .num_of_idx = 2,
+               .no_multi_nss = true,
+       },
+       {
+               .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_NON_OFDMA },
+               .num_of_idx = 14,
+       },
+       {
+               .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_NON_OFDMA },
+               .num_of_idx = RTW89_RATE_HEDCM_NUM,
+       },
+       {
+               .init = { .rs = RTW89_RS_MCS, .ofdma = RTW89_OFDMA },
+               .num_of_idx = 14,
+       },
+       {
+               .init = { .rs = RTW89_RS_HEDCM, .ofdma = RTW89_OFDMA },
+               .num_of_idx = RTW89_RATE_HEDCM_NUM,
+       },
+};
+
+static
+void __phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev, u8 band, u8 bw,
+                              u8 nss, u32 *addr, enum rtw89_phy_idx phy_idx)
+{
+       const struct rtw89_byr_spec_ent_be *ent;
+       struct rtw89_rate_desc desc;
+       int pos = 0;
+       int i, j;
+       u32 val;
+       s8 v[4];
+
+       for (i = 0; i < ARRAY_SIZE(rtw89_byr_spec_be); i++) {
+               ent = &rtw89_byr_spec_be[i];
+
+               if (bw > RTW89_CHANNEL_WIDTH_40 && ent->no_over_bw40)
+                       continue;
+               if (nss > RTW89_NSS_1 && ent->no_multi_nss)
+                       continue;
+
+               desc = ent->init;
+               desc.nss = nss;
+               for (j = 0; j < ent->num_of_idx; j++, desc.idx++) {
+                       v[pos] = rtw89_phy_read_txpwr_byrate(rtwdev, band, bw,
+                                                            &desc);
+                       pos = (pos + 1) % 4;
+                       if (pos)
+                               continue;
+
+                       val = u32_encode_bits(v[0], GENMASK(7, 0)) |
+                             u32_encode_bits(v[1], GENMASK(15, 8)) |
+                             u32_encode_bits(v[2], GENMASK(23, 16)) |
+                             u32_encode_bits(v[3], GENMASK(31, 24));
+
+                       rtw89_mac_txpwr_write32(rtwdev, phy_idx, *addr, val);
+                       *addr += 4;
+               }
+       }
+}
+
+static void rtw89_phy_set_txpwr_byrate_be(struct rtw89_dev *rtwdev,
+                                         const struct rtw89_chan *chan,
+                                         enum rtw89_phy_idx phy_idx)
+{
+       u32 addr = R_BE_PWR_BY_RATE;
+       u8 band = chan->band_type;
+       u8 bw, nss;
+
+       rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
+                   "[TXPWR] set txpwr byrate on band %d\n", band);
+
+       for (bw = 0; bw <= RTW89_CHANNEL_WIDTH_320; bw++)
+               for (nss = 0; nss <= RTW89_NSS_2; nss++)
+                       __phy_set_txpwr_byrate_be(rtwdev, band, bw, nss,
+                                                 &addr, phy_idx);
+}
+
 const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
        .cr_base = 0x20000,
        .ccx = &rtw89_ccx_regs_be,
        .physts = &rtw89_physts_regs_be,
+
+       .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_be,
 };
 EXPORT_SYMBOL(rtw89_phy_gen_be);

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 7c74afd8289c7d826021b8b74c89b0bb6e4c0db7..9e40fb28486ee4f9371e48dfba3875b867085ba4 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -3941,6 +3941,8 @@
 #define R_BE_PWR_MODULE 0x11900
 #define R_BE_PWR_MODULE_C1 0x15900
 
+#define R_BE_PWR_BY_RATE 0x11E00
+
 #define CMAC1_START_ADDR_BE 0x14000
 #define CMAC1_END_ADDR_BE 0x17FFF