powerpc/mm: Switch obsolete dssall to .long

The dssall ("Data Stream Stop All") instruction is obsolete altogether
with other Data Cache Instructions since ISA 2.03 (year 2006).

LLVM IAS does not support it but PPC970 seems to be using it.
This switches dssall to .long as there is no much point in fixing LLVM.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211221055904.555763-6-aik@ozlabs.ru

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index f50213e2a3e02b82de3f70d11fe51e8081290ecb..9fe3223e7820df65f3721a6edeed16f7abddb2fa 100644 (file)
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -249,6 +249,7 @@
 #define PPC_INST_COPY                  0x7c20060c
 #define PPC_INST_DCBA                  0x7c0005ec
 #define PPC_INST_DCBA_MASK             0xfc0007fe
+#define PPC_INST_DSSALL                        0x7e00066c
 #define PPC_INST_ISEL                  0x7c00001e
 #define PPC_INST_ISEL_MASK             0xfc00003e
 #define PPC_INST_LSWI                  0x7c0004aa
@@ -577,6 +578,7 @@
 #define        PPC_DCBZL(a, b)         stringify_in_c(.long PPC_RAW_DCBZL(a, b))
 #define        PPC_DIVDE(t, a, b)      stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
 #define        PPC_DIVDEU(t, a, b)     stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
+#define PPC_DSSALL             stringify_in_c(.long PPC_INST_DSSALL)
 #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
 #define PPC_STQCX(t, a, b)     stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
 #define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))

diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 1f835539fda420d7f6d0005a7da502da7d42c473..4ad79eb638c62bce1db8d22b639a97cbb022d111 100644 (file)
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -82,7 +82,7 @@ void power4_idle(void)
                return;
 
        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-               asm volatile("DSSALL ; sync" ::: "memory");
+               asm volatile(PPC_DSSALL " ; sync" ::: "memory");
 
        power4_idle_nap();
 

diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 13cad9297d8222fb5f37605f5798909095296991..3c097356366b8c1c165d5113414ef571f6f7fa95 100644 (file)
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -129,7 +129,7 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
        mtspr   SPRN_HID0,r4
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        lwz     r8,TI_LOCAL_FLAGS(r2)   /* set napping bit */

diff --git a/arch/powerpc/kernel/l2cr_6xx.S b/arch/powerpc/kernel/l2cr_6xx.S
index 225511d73bef560b536ab8bc2d9abc4a2b17b88c..f2e03ed423d0fc1cc660afc032899161e34acf3b 100644 (file)
--- a/arch/powerpc/kernel/l2cr_6xx.S
+++ b/arch/powerpc/kernel/l2cr_6xx.S
@@ -96,7 +96,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
 
        /* Stop DST streams */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 
@@ -292,7 +292,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
        isync
 
        /* Stop DST streams */
-       DSSALL
+       PPC_DSSALL
        sync
 
        /* Get the current enable bit of the L3CR into r4 */
@@ -401,7 +401,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
 _GLOBAL(__flush_disable_L1)
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        sync
 

diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index f73f4d72fea43570a76eedafbebd5d00750ed49e..e0cbd63007f21e01e9ee8c444672f97fcfca65f9 100644 (file)
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -181,7 +181,7 @@ _GLOBAL(swsusp_arch_resume)
 #ifdef CONFIG_ALTIVEC
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
        sync

diff --git a/arch/powerpc/kernel/swsusp_asm64.S b/arch/powerpc/kernel/swsusp_asm64.S
index 96bb20715aa9c4cac8b34d64f20ea6c20a9d60a4..9f1903c7f54092f66a36055d72bccdf9a5b667f9 100644 (file)
--- a/arch/powerpc/kernel/swsusp_asm64.S
+++ b/arch/powerpc/kernel/swsusp_asm64.S
@@ -141,7 +141,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_LPAR)
 _GLOBAL(swsusp_arch_resume)
        /* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        sync
 

diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c
index 735c36f263882c5184965a9620695b084ca510e2..1fb9c99f86797a3211db4291df9cd4697b4c005a 100644 (file)
--- a/arch/powerpc/mm/mmu_context.c
+++ b/arch/powerpc/mm/mmu_context.c
@@ -90,7 +90,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
         * context
         */
        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-               asm volatile ("dssall");
+               asm volatile (PPC_DSSALL);
 
        if (!new_on_cpu)
                membarrier_arch_switch_mm(prev, next, tsk);

diff --git a/arch/powerpc/platforms/powermac/cache.S b/arch/powerpc/platforms/powermac/cache.S
index ced2254154860af64c21c69a733c9e458558b050..b8ae56e9f41466c8a6c28bb688912e69ed6fee16 100644 (file)
--- a/arch/powerpc/platforms/powermac/cache.S
+++ b/arch/powerpc/platforms/powermac/cache.S
@@ -48,7 +48,7 @@ flush_disable_75x:
 
        /* Stop DST streams */
 BEGIN_FTR_SECTION
-       DSSALL
+       PPC_DSSALL
        sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 
@@ -197,7 +197,7 @@ flush_disable_745x:
        isync
 
        /* Stop prefetch streams */
-       DSSALL
+       PPC_DSSALL
        sync
 
        /* Disable L2 prefetching */