ARC: mm: fix new code about cache aliasing

Manual/partial revert of 8690bbcf3b70 ("Introduce cpu_dcache_is_aliasing() across all architectures")

Current generation of ARCv2/ARCv3 based HSxx cores are only PIPT (to software
at least).

Legacy ARC700 cpus could be VIPT aliasing (based on cache geometry and
PAGE_SIZE) [1] however recently that support was ripped out so VIPT aliasing
cache is not relevant to ARC anymore.

[1] http://lists.infradead.org/pipermail/linux-snps-arc/2023-February/006899.html

Acked-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 99d2845f3feb954d495253e938fb4dec73be1720..4092bec198beca44d6c019643db6829293f7320d 100644 (file)
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -6,7 +6,6 @@
 config ARC
        def_bool y
        select ARC_TIMERS
-       select ARCH_HAS_CPU_CACHE_ALIASING
        select ARCH_HAS_CACHE_LINE_SIZE
        select ARCH_HAS_DEBUG_VM_PGTABLE
        select ARCH_HAS_DMA_PREP_COHERENT

diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
deleted file mode 100644 (file)
index 05fc7ed..0000000
--- a/arch/arc/include/asm/cachetype.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARC_CACHETYPE_H
-#define __ASM_ARC_CACHETYPE_H
-
-#include <linux/types.h>
-
-#define cpu_dcache_is_aliasing()       true
-
-#endif