drm/amdgpu: nuke dynamic gfx scratch reg allocation

It's over a decade ago that this was actually used for more than ring and
IB tests. Just use the static register directly where needed and nuke the
now useless infrastructure.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 5d6b04fc6206ef9dc8a66b8722769960c54a20b6..ede2fa56f6c90d92e19b9b02ef1c5203f24afdc1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -98,42 +98,6 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
                        adev->gfx.me.queue_bitmap);
 }
 
-/**
- * amdgpu_gfx_scratch_get - Allocate a scratch register
- *
- * @adev: amdgpu_device pointer
- * @reg: scratch register mmio offset
- *
- * Allocate a CP scratch register for use by the driver (all asics).
- * Returns 0 on success or -EINVAL on failure.
- */
-int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
-{
-       int i;
-
-       i = ffs(adev->gfx.scratch.free_mask);
-       if (i != 0 && i <= adev->gfx.scratch.num_reg) {
-               i--;
-               adev->gfx.scratch.free_mask &= ~(1u << i);
-               *reg = adev->gfx.scratch.reg_base + i;
-               return 0;
-       }
-       return -EINVAL;
-}
-
-/**
- * amdgpu_gfx_scratch_free - Free a scratch register
- *
- * @adev: amdgpu_device pointer
- * @reg: scratch register mmio offset
- *
- * Free a CP scratch register allocated for use by the driver (all asics)
- */
-void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
-{
-       adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
-}
-
 /**
  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
  *

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 45522609d4b46f95b748e4fac5c1a0adb23e38a9..53526ffb2ce1601e57f5570ac442d1ed8fe5d27e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -110,15 +110,6 @@ struct amdgpu_kiq {
        const struct kiq_pm4_funcs *pmf;
 };
 
-/*
- * GPU scratch registers structures, functions & helpers
- */
-struct amdgpu_scratch {
-       unsigned                num_reg;
-       uint32_t                reg_base;
-       uint32_t                free_mask;
-};
-
 /*
  * GFX configurations
  */
@@ -288,7 +279,6 @@ struct amdgpu_gfx {
        struct amdgpu_mec               mec;
        struct amdgpu_kiq               kiq;
        struct amdgpu_imu               imu;
-       struct amdgpu_scratch           scratch;
        bool                            rs64_enable; /* firmware format */
        const struct firmware           *me_fw; /* ME firmware */
        uint32_t                        me_fw_version;
@@ -376,9 +366,6 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
        return (u32)((1ULL << bit_width) - 1);
 }
 
-int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
-void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
-
 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
                                 unsigned max_sh);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 64d36622ee2322b25a328a57042fb3300a9954ad..4b66b9c93754ba30f41841695ebb7633731ae018 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3744,13 +3744,6 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
        gfx_v10_0_init_spm_golden_registers(adev);
 }
 
-static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
                                       bool wc, uint32_t reg, uint32_t val)
 {
@@ -3787,34 +3780,26 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r) {
-               DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
-               return r;
-       }
-
-       WREG32(scratch, 0xCAFEDEAD);
-
+       WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r) {
                DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
                          ring->idx, r);
-               amdgpu_gfx_scratch_free(adev, scratch);
                return r;
        }
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-       amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+                         PACKET3_SET_UCONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(scratch);
+               tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
                if (tmp == 0xDEADBEEF)
                        break;
                if (amdgpu_emu_mode == 1)
@@ -3826,8 +3811,6 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
 
-       amdgpu_gfx_scratch_free(adev, scratch);
-
        return r;
 }
 
@@ -4852,8 +4835,6 @@ static int gfx_v10_0_sw_init(void *handle)
 
        adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
-       gfx_v10_0_scratch_init(adev);
-
        r = gfx_v10_0_me_init(adev);
        if (r)
                return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 7c75fe51ec208f3626f18028ab93d35a7d297beb..9416dc93e4569f123994873965c9164fb7e46116 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -297,13 +297,6 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
        gfx_v11_0_init_spm_golden_registers(adev);
 }
 
-static void gfx_v11_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
                                       bool wc, uint32_t reg, uint32_t val)
 {
@@ -340,24 +333,16 @@ static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
+       uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r) {
-               DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
-               return r;
-       }
-
        WREG32(scratch, 0xCAFEDEAD);
-
        r = amdgpu_ring_alloc(ring, 5);
        if (r) {
                DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
                          ring->idx, r);
-               amdgpu_gfx_scratch_free(adev, scratch);
                return r;
        }
 
@@ -365,7 +350,8 @@ static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
                gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
        } else {
                amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-               amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+               amdgpu_ring_write(ring, scratch -
+                                 PACKET3_SET_UCONFIG_REG_START);
                amdgpu_ring_write(ring, 0xDEADBEEF);
        }
        amdgpu_ring_commit(ring);
@@ -382,9 +368,6 @@ static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
-
-       amdgpu_gfx_scratch_free(adev, scratch);
-
        return r;
 }
 
@@ -1631,8 +1614,6 @@ static int gfx_v11_0_sw_init(void *handle)
 
        adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
-       gfx_v11_0_scratch_init(adev);
-
        if (adev->gfx.imu.funcs) {
                if (adev->gfx.imu.funcs->init_microcode) {
                        r = adev->gfx.imu.funcs->init_microcode(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 29a91b320d4fe3a482a31e56add686aceb2aa475..204b246f0e3f94d967694fe82d34bbe711dfaa60 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1778,39 +1778,26 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
        udelay(50);
 }
 
-
-static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
 
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
-               goto error_free_scratch;
+               return r;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
+       amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(scratch);
+               tmp = RREG32(mmSCRATCH_REG0);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
@@ -1818,9 +1805,6 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
-
-error_free_scratch:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -1903,50 +1887,42 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 {
        struct amdgpu_device *adev = ring->adev;
-       struct amdgpu_ib ib;
        struct dma_fence *f = NULL;
-       uint32_t scratch;
+       struct amdgpu_ib ib;
        uint32_t tmp = 0;
        long r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
        memset(&ib, 0, sizeof(ib));
-       r = amdgpu_ib_get(adev, NULL, 256,
-                                       AMDGPU_IB_POOL_DIRECT, &ib);
+       r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
        if (r)
-               goto err1;
+               return r;
 
        ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
-       ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
+       ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
        ib.ptr[2] = 0xDEADBEEF;
        ib.length_dw = 3;
 
        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
        if (r)
-               goto err2;
+               goto error;
 
        r = dma_fence_wait_timeout(f, false, timeout);
        if (r == 0) {
                r = -ETIMEDOUT;
-               goto err2;
+               goto error;
        } else if (r < 0) {
-               goto err2;
+               goto error;
        }
-       tmp = RREG32(scratch);
+       tmp = RREG32(mmSCRATCH_REG0);
        if (tmp == 0xDEADBEEF)
                r = 0;
        else
                r = -EINVAL;
 
-err2:
+error:
        amdgpu_ib_free(adev, &ib, NULL);
        dma_fence_put(f);
-err1:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -3094,8 +3070,6 @@ static int gfx_v6_0_sw_init(void *handle)
        if (r)
                return r;
 
-       gfx_v6_0_scratch_init(adev);
-
        r = gfx_v6_0_init_microcode(adev);
        if (r) {
                DRM_ERROR("Failed to load gfx firmware!\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index ac3f2dbba7260f90cc98a3132e3c4770a62a5190..0f2976507e484de148409c2a5a664815eb3d1775 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2049,26 +2049,6 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
        udelay(50);
 }
 
-/*
- * GPU scratch registers helpers function.
- */
-/**
- * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the number and offset of the CP scratch registers.
- * NOTE: use of CP scratch registers is a legacy interface and
- * is not used by default on newer asics (r6xx+).  On newer asics,
- * memory buffers are used for fences rather than scratch regs.
- */
-static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 /**
  * gfx_v7_0_ring_test_ring - basic gfx ring test
  *
@@ -2082,36 +2062,28 @@ static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
-               goto error_free_scratch;
+               return r;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-       amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(scratch);
+               tmp = RREG32(mmSCRATCH_REG0);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
        }
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
-
-error_free_scratch:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -2355,48 +2327,40 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_ib ib;
        struct dma_fence *f = NULL;
-       uint32_t scratch;
        uint32_t tmp = 0;
        long r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
        memset(&ib, 0, sizeof(ib));
-       r = amdgpu_ib_get(adev, NULL, 256,
-                                       AMDGPU_IB_POOL_DIRECT, &ib);
+       r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
        if (r)
-               goto err1;
+               return r;
 
        ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-       ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
+       ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
        ib.ptr[2] = 0xDEADBEEF;
        ib.length_dw = 3;
 
        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
        if (r)
-               goto err2;
+               goto error;
 
        r = dma_fence_wait_timeout(f, false, timeout);
        if (r == 0) {
                r = -ETIMEDOUT;
-               goto err2;
+               goto error;
        } else if (r < 0) {
-               goto err2;
+               goto error;
        }
-       tmp = RREG32(scratch);
+       tmp = RREG32(mmSCRATCH_REG0);
        if (tmp == 0xDEADBEEF)
                r = 0;
        else
                r = -EINVAL;
 
-err2:
+error:
        amdgpu_ib_free(adev, &ib, NULL);
        dma_fence_put(f);
-err1:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -4489,8 +4453,6 @@ static int gfx_v7_0_sw_init(void *handle)
        if (r)
                return r;
 
-       gfx_v7_0_scratch_init(adev);
-
        r = gfx_v7_0_init_microcode(adev);
        if (r) {
                DRM_ERROR("Failed to load gfx firmware!\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e4e779a19c2035af8490c8ca57e863ec67531bc8..90f64219d291b1cd865b5beadb7e598292ff1d6d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -835,37 +835,25 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
        }
 }
 
-static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
-               goto error_free_scratch;
+               return r;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-       amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(scratch);
+               tmp = RREG32(mmSCRATCH_REG0);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
@@ -874,8 +862,6 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
 
-error_free_scratch:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -2000,8 +1986,6 @@ static int gfx_v8_0_sw_init(void *handle)
 
        adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
-       gfx_v8_0_scratch_init(adev);
-
        r = gfx_v8_0_init_microcode(adev);
        if (r) {
                DRM_ERROR("Failed to load gfx firmware!\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 06182b7e43510f958364bf96ab25e75442435811..83639b5ea6a9949a616016c89358ddbf3584653b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -950,13 +950,6 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
                                                (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 }
 
-static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
-{
-       adev->gfx.scratch.num_reg = 8;
-       adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
-       adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
-}
-
 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
                                       bool wc, uint32_t reg, uint32_t val)
 {
@@ -994,27 +987,23 @@ static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 {
        struct amdgpu_device *adev = ring->adev;
-       uint32_t scratch;
        uint32_t tmp = 0;
        unsigned i;
        int r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r)
-               return r;
-
-       WREG32(scratch, 0xCAFEDEAD);
+       WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
-               goto error_free_scratch;
+               return r;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
-       amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+       amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+                         PACKET3_SET_UCONFIG_REG_START);
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(scratch);
+               tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
                if (tmp == 0xDEADBEEF)
                        break;
                udelay(1);
@@ -1022,9 +1011,6 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 
        if (i >= adev->usec_timeout)
                r = -ETIMEDOUT;
-
-error_free_scratch:
-       amdgpu_gfx_scratch_free(adev, scratch);
        return r;
 }
 
@@ -2338,8 +2324,6 @@ static int gfx_v9_0_sw_init(void *handle)
 
        adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 
-       gfx_v9_0_scratch_init(adev);
-
        r = gfx_v9_0_init_microcode(adev);
        if (r) {
                DRM_ERROR("Failed to load gfx firmware!\n");