arm64: dts: imx8qm-mek: add flexspi0 support

Add flexspi0 support for imx8qm-mek board.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 66e0400d7bf8ae7fcc26f3cbb31c21d60e49de92..5c6b39c6933fc4f108e20c98b0f9a03706e583f6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -100,6 +100,22 @@
        };
 };
 
+&flexspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_flexspi0>;
+       status = "okay";
+
+       flash0: flash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               spi-max-frequency = <133000000>;
+               spi-tx-bus-width = <8>;
+               spi-rx-bus-width = <8>;
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
@@ -198,6 +214,27 @@
                >;
        };
 
+       pinctrl_flexspi0: flexspi0grp {
+               fsl,pins = <
+                       IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
+                       IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
+                       IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
+                       IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
+                       IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
+                       IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
+                       IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B     0x06000021
+                       IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
+                       IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
+                       IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
+                       IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
+                       IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
+                       IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
+                       IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
+                       IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
+                       IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B     0x06000021
+               >;
+       };
+
        pinctrl_lpuart0: lpuart0grp {
                fsl,pins = <
                        IMX8QM_UART0_RX_DMA_UART0_RX                            0x06000020