drm/amd/display: fix pipe topology logging error

[why]
There is a logging error in the recently added pipe topology log.
If the plane with index 0 uses MPC combine, the log shows that
as two separate planes.

[how]
Initialize plane idx as -1 and increment plane idx before logging
any primary dpp pipes of a plane.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f32337122f5b719b47889220314746b791ac4c20..30424ba7761d21473ccee8aa6f42dd628d138a36 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1996,8 +1996,8 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
                slice_count = resource_get_opp_heads_for_otg_master(otg_master,
                                &state->res_ctx, opp_heads);
                for (slice_idx = 0; slice_idx < slice_count; slice_idx++) {
+                       plane_idx = -1;
                        if (opp_heads[slice_idx]->plane_state) {
-                               plane_idx = 0;
                                dpp_count = resource_get_dpp_pipes_for_opp_head(
                                                opp_heads[slice_idx],
                                                &state->res_ctx,
@@ -2005,15 +2005,14 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state)
                                for (dpp_idx = 0; dpp_idx < dpp_count; dpp_idx++) {
                                        is_primary = !dpp_pipes[dpp_idx]->top_pipe ||
                                                        dpp_pipes[dpp_idx]->top_pipe->plane_state != dpp_pipes[dpp_idx]->plane_state;
+                                       if (is_primary)
+                                               plane_idx++;
                                        resource_log_pipe(dc, dpp_pipes[dpp_idx],
                                                        stream_idx, slice_idx,
                                                        plane_idx, slice_count,
                                                        is_primary);
-                                       if (is_primary)
-                                               plane_idx++;
                                }
                        } else {
-                               plane_idx = -1;
                                resource_log_pipe(dc, opp_heads[slice_idx],
                                                stream_idx, slice_idx, plane_idx,
                                                slice_count, true);