KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it
authorNicholas Piggin <npiggin@gmail.com>
Tue, 23 Nov 2021 09:52:12 +0000 (19:52 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Wed, 24 Nov 2021 10:09:00 +0000 (21:09 +1100)
Use CPU_FTR_P9_RADIX_PREFETCH_BUG to apply the workaround, to test for
DD2.1 and below processors. This saves a mtSPR in guest entry.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211123095231.1036501-35-npiggin@gmail.com
arch/powerpc/kvm/book3s_hv.c
arch/powerpc/kvm/book3s_hv_p9_entry.c

index c14467cf23d33be106f21e4eefc2852f09f764ee..3795080d54038a32dfc63d36a4a5343240e787ae 100644 (file)
@@ -1590,7 +1590,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
                unsigned long vsid;
                long err;
 
-               if (vcpu->arch.fault_dsisr == HDSISR_CANARY) {
+               if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG) &&
+                   unlikely(vcpu->arch.fault_dsisr == HDSISR_CANARY)) {
                        r = RESUME_GUEST; /* Just retry if it's the canary */
                        break;
                }
index 619bbcd47b928ac63ac8904ce18346b6f54775cf..67f57b03a896616944ab83d632e753677e20f7c4 100644 (file)
@@ -683,9 +683,11 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc
         * HDSI which should correctly update the HDSISR the second time HDSI
         * entry.
         *
-        * Just do this on all p9 processors for now.
+        * The "radix prefetch bug" test can be used to test for this bug, as
+        * it also exists fo DD2.1 and below.
         */
-       mtspr(SPRN_HDSISR, HDSISR_CANARY);
+       if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
+               mtspr(SPRN_HDSISR, HDSISR_CANARY);
 
        mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
        mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);