drm/radeon/si: fix define for MC_SEQ_TRAIN_WAKEUP_CNTL

Typo in the register offset.

Noticed-by: Sylvain BERTRAND <sylware@legeek.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 307ffdfd644c2f3f2161e6d4e6528dabf89d23fa..5691a7c306867ff4759a67ca250bba4955545d91 100644 (file)
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -478,7 +478,7 @@
 #define                STATE3_MASK                             (0x1f << 15)
 #define                STATE3_SHIFT                            15
 
-#define        MC_SEQ_TRAIN_WAKEUP_CNTL                        0x2808
+#define        MC_SEQ_TRAIN_WAKEUP_CNTL                        0x28e8
 #define                TRAIN_DONE_D0                           (1 << 30)
 #define                TRAIN_DONE_D1                           (1 << 31)