drm/xe/gsc: Implement WA 14018094691

The WA states that we need to keep the primary GT powered up during GSC
load to allow the GSC FW to access its registers. We also need to make
sure that one of the registers is locked before starting the load.

v2: fix location of register def (Matt)

Bspec: 55928
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240326224456.518548-1-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 65af9fe95db5b4a02990282eed70681fdf9e4049..d5b21f03beaaa4f6110c36b95a5d46d388ec522d 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -370,6 +370,9 @@
 #define RT_CTRL                                        XE_REG_MCR(0xe530)
 #define   DIS_NULL_QUERY                       REG_BIT(10)
 
+#define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534)
+#define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT        REG_BIT(31)
+
 #define XEHP_HDC_CHICKEN0                                      XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 11)
 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES     REG_BIT(3)

diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 8339b0b49dfb754614230280c700436d766c7378..92dc442a5114f6cd084ab5a7a9a8a8a22387ed4c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -17,6 +17,7 @@
 #include "xe_gsc_proxy.h"
 #include "xe_gsc_submit.h"
 #include "xe_gt.h"
+#include "xe_gt_mcr.h"
 #include "xe_gt_printk.h"
 #include "xe_huc.h"
 #include "xe_map.h"
@@ -252,9 +253,30 @@ static int gsc_upload(struct xe_gsc *gsc)
 static int gsc_upload_and_init(struct xe_gsc *gsc)
 {
        struct xe_gt *gt = gsc_to_gt(gsc);
+       struct xe_tile *tile = gt_to_tile(gt);
        int ret;
 
+       if (XE_WA(gt, 14018094691)) {
+               ret = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
+
+               /*
+                * If the forcewake fails we want to keep going, because the worst
+                * case outcome in failing to apply the WA is that PXP won't work,
+                * which is not fatal. We still throw a warning so the issue is
+                * seen if it happens.
+                */
+               xe_gt_WARN_ON(tile->primary_gt, ret);
+
+               xe_gt_mcr_multicast_write(tile->primary_gt,
+                                         EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK,
+                                         EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT);
+       }
+
        ret = gsc_upload(gsc);
+
+       if (XE_WA(gt, 14018094691))
+               xe_force_wake_put(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL);
+
        if (ret)
                return ret;
 

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 48cdba1cbf95e93453442a28c5764688c308c5a3..68600cdead84e6cc2d8942e736afd1dcee417d88 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -19,3 +19,4 @@
                GRAPHICS_VERSION_RANGE(1270, 1274)
                MEDIA_VERSION(1300)
                PLATFORM(DG2)
+14018094691    GRAPHICS_VERSION(2004)