drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid
authorLikun Gao <Likun.Gao@amd.com>
Fri, 23 Aug 2019 06:35:45 +0000 (14:35 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 3 Jun 2020 17:52:04 +0000 (13:52 -0400)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
drivers/gpu/drm/amd/include/soc15_ih_clientid.h

index b9b218ba01baf99f005dbd2ed7fa25c767972a00..5a47f105cd14a0b3ab2d857687a5e13a96e468f4 100644 (file)
@@ -1166,7 +1166,7 @@ static int sdma_v5_2_sw_init(void *handle)
                return r;
 
        /* SDMA trap event */
-       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3,
+       r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid,
                              SDMA3_5_0__SRCID__SDMA_TRAP,
                              &adev->sdma.trap_irq);
        if (r)
@@ -1408,7 +1408,7 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
                        break;
                }
                break;
-       case SOC15_IH_CLIENTID_SDMA3:
+       case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
                switch (entry->ring_id) {
                case 0:
                        amdgpu_fence_process(&adev->sdma.instance[3].ring);
index 1794ad1fc4fcc5ddc3bc0e69a1643454d8ffa68b..fb67bb55ed79334f5cce3ac30878f8b6cb419990 100644 (file)
@@ -66,6 +66,7 @@ enum soc15_ih_clientid {
        SOC15_IH_CLIENTID_VCN1          = SOC15_IH_CLIENTID_UVD1,
        SOC15_IH_CLIENTID_SDMA2         = SOC15_IH_CLIENTID_ACP,
        SOC15_IH_CLIENTID_SDMA3         = SOC15_IH_CLIENTID_DCE,
+       SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid    = SOC15_IH_CLIENTID_ISP,
        SOC15_IH_CLIENTID_SDMA4         = SOC15_IH_CLIENTID_ISP,
        SOC15_IH_CLIENTID_SDMA5         = SOC15_IH_CLIENTID_VCE0,
        SOC15_IH_CLIENTID_SDMA6         = SOC15_IH_CLIENTID_XDMA,