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Intel cache info, by Filip Navara.
author
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 13 Sep 2007 02:21:28 +0000
(
02:21
+0000)
committer
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 13 Sep 2007 02:21:28 +0000
(
02:21
+0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3162
c046a42c
-6fe2-441c-8c8c-
71466251a162
target-i386/helper.c
patch
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diff --git
a/target-i386/helper.c
b/target-i386/helper.c
index 3c051b9ea3c41c55309c5f66cc0c2035e0b49bb7..64c3a613256c925a8344e378f7287c2a8422977d 100644
(file)
--- a/
target-i386/helper.c
+++ b/
target-i386/helper.c
@@
-1657,10
+1657,10
@@
void helper_cpuid(void)
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
- EAX =
0x41060
1;
+ EAX = 1;
EBX = 0;
ECX = 0;
- EDX = 0;
+ EDX = 0
x2c307d
;
break;
case 0x80000000:
EAX = env->cpuid_xlevel;