return float32_to_float64(src, &env->fp_status);
}
-float32 helper_fqtos(CPUSPARCState *env)
+float32 helper_fqtos(CPUSPARCState *env, Int128 src)
{
- return float128_to_float32(QT1, &env->fp_status);
+ return float128_to_float32(f128_in(src), &env->fp_status);
}
void helper_fstoq(CPUSPARCState *env, float32 src)
return float64_to_int32_round_to_zero(src, &env->fp_status);
}
-int32_t helper_fqtoi(CPUSPARCState *env)
+int32_t helper_fqtoi(CPUSPARCState *env, Int128 src)
{
- return float128_to_int32_round_to_zero(QT1, &env->fp_status);
+ return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status);
}
#ifdef TARGET_SPARC64
#endif
DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64)
DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32)
-DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env)
+DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128)
DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32)
DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env)
DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64)
DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32)
DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64)
-DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env)
+DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32)
DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64)
TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq)
static bool do_env_fq(DisasContext *dc, arg_r_r *a,
- void (*func)(TCGv_i32, TCGv_env))
+ void (*func)(TCGv_i32, TCGv_env, TCGv_i128))
{
+ TCGv_i128 src;
TCGv_i32 dst;
if (gen_trap_ifnofpu(dc)) {
}
gen_op_clear_ieee_excp_and_FTT();
- gen_op_load_fpr_QT1(QFPREG(a->rs));
+ src = gen_load_fpr_Q(dc, a->rs);
dst = tcg_temp_new_i32();
- func(dst, tcg_env);
+ func(dst, tcg_env, src);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_store_fpr_F(dc, a->rd, dst);
return advance_pc(dc);