*/
#define WR_1 0x100
+/* 16 MiB max in 3 byte address mode */
+#define MAX_3BYTES_SIZE 0x1000000
+
typedef struct FlashPartInfo {
const char *part_name;
/* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
ERASE_32K = 0x52,
ERASE_SECTOR = 0xd8,
+ EXTEND_ADDR_READ = 0xC8,
+ EXTEND_ADDR_WRITE = 0xC5,
+
RESET_ENABLE = 0x66,
RESET_MEMORY = 0x99,
} FlashCMD;
uint64_t cur_addr;
bool write_enable;
bool reset_enable;
+ uint8_t ear;
int64_t dirty_page;
s->cur_addr = s->data[0] << 16;
s->cur_addr |= s->data[1] << 8;
s->cur_addr |= s->data[2];
+ s->cur_addr += (s->ear & 0x3) * MAX_3BYTES_SIZE;
s->state = STATE_IDLE;
s->write_enable = false;
}
break;
+ case EXTEND_ADDR_WRITE:
+ s->ear = s->data[0];
+ break;
default:
break;
}
{
s->cmd_in_progress = NOP;
s->cur_addr = 0;
+ s->ear = 0;
s->len = 0;
s->needed_bytes = 0;
s->pos = 0;
break;
case NOP:
break;
+ case EXTEND_ADDR_READ:
+ s->data[0] = s->ear;
+ s->pos = 0;
+ s->len = 1;
+ s->state = STATE_READING_DATA;
+ break;
+ case EXTEND_ADDR_WRITE:
+ if (s->write_enable) {
+ s->needed_bytes = 1;
+ s->pos = 0;
+ s->len = 0;
+ s->state = STATE_COLLECTING_DATA;
+ }
+ break;
case RESET_ENABLE:
s->reset_enable = true;
break;
VMSTATE_UINT64(cur_addr, Flash),
VMSTATE_BOOL(write_enable, Flash),
VMSTATE_BOOL_V(reset_enable, Flash, 2),
+ VMSTATE_UINT8_V(ear, Flash, 2),
VMSTATE_END_OF_LIST()
}
};