drm/amd/powerplay: tag swSMU code layers
authorEvan Quan <evan.quan@amd.com>
Wed, 8 Jul 2020 04:45:00 +0000 (12:45 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 21 Jul 2020 19:37:38 +0000 (15:37 -0400)
Per designs, the swSMU code is separated into four layers. And the typical
calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c
-> smu_cmn.c. Compile errors will come out for any violations. This can
help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c ->
amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
13 files changed:
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
drivers/gpu/drm/amd/powerplay/smu_cmn.c
drivers/gpu/drm/amd/powerplay/smu_cmn.h
drivers/gpu/drm/amd/powerplay/smu_internal.h
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
drivers/gpu/drm/amd/powerplay/smu_v12_0.c

index 0d90cd76d30fa5bdce3897848580a41efc909383..b197dcaed0649b55250764203385becbadaeecb4 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#define SWSMU_CODE_LAYER_L1
+
 #include <linux/firmware.h>
 #include <linux/pci.h>
 
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
 #include "smu_internal.h"
-#include "smu_v11_0.h"
-#include "smu_v12_0.h"
 #include "atom.h"
 #include "arcturus_ppt.h"
 #include "navi10_ppt.h"
index 3febd6a61f78eb8acb25818e884485d8184e9329..9b68760dd35be151fcd290d97a52c757822e74bc 100644 (file)
  *
  */
 
+#define SWSMU_CODE_LAYER_L2
+
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "amdgpu_atombios.h"
index a152ea0cab7489a3b1ffdd8d57aab33a0bee93cc..896b443f1ce854a7a14d22a5c1f801392e22992b 100644 (file)
@@ -653,6 +653,7 @@ enum smu_cmn2asic_mapping_type {
 #define WORKLOAD_MAP(profile, workload) \
        [profile] = {1, (workload)}
 
+#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
 int smu_load_microcode(struct smu_context *smu);
 
 int smu_check_fw_status(struct smu_context *smu);
@@ -790,3 +791,4 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
 
 #endif
+#endif
index b695b8800b3b2dcbd1da10ad61d0006d4ec03049..b18ee5837f50622e0ce451d088ff43c635c210ff 100644 (file)
@@ -134,6 +134,8 @@ enum smu_v11_0_baco_seq {
        BACO_SEQ_COUNT,
 };
 
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
 int smu_v11_0_init_microcode(struct smu_context *smu);
 
 void smu_v11_0_fini_microcode(struct smu_context *smu);
@@ -263,3 +265,4 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
                                  uint32_t *max_value);
 
 #endif
+#endif
index 52cdd6a0f99a7624ea3eb7d635cee5a898c218fc..02de3b6199e5332afe1b7308f5dce9e12c27ed5e 100644 (file)
@@ -31,6 +31,8 @@
 #define MP1_Public                     0x03b00000
 #define MP1_SRAM                       0x03c00004
 
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
 int smu_v12_0_check_fw_status(struct smu_context *smu);
 
 int smu_v12_0_check_fw_version(struct smu_context *smu);
@@ -59,3 +61,4 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
 int smu_v12_0_set_driver_table_location(struct smu_context *smu);
 
 #endif
+#endif
index 47aa497591ecca72605de43c378893e4966d8a80..2512ba17eaaf899edb664a42ff927234c94dae5e 100644 (file)
  *
  */
 
+#define SWSMU_CODE_LAYER_L2
+
 #include <linux/firmware.h>
 #include <linux/pci.h>
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "amdgpu_atombios.h"
index 7e93be4a97ffc1851dc18c06f903381112877826..575ae4be98a2917b02f1ed50bb20f164d65e9362 100644 (file)
  *
  */
 
+#define SWSMU_CODE_LAYER_L2
+
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "smu_v12_0_ppsmc.h"
 #include "smu12_driver_if.h"
 #include "smu_v12_0.h"
index 25fe82b41ce5266b00b54037a4ffd621d6950069..cae8e776fafebbb5638d70bd15307727f7fcd489 100644 (file)
  *
  */
 
+#define SWSMU_CODE_LAYER_L2
+
 #include <linux/firmware.h>
 #include <linux/pci.h>
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "amdgpu_atombios.h"
index 4084c707c04a12e62dec82e22418dba725d49713..be4b678d0e60130f48b7205d8c8d00f771a65519 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#define SWSMU_CODE_LAYER_L4
+
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
 #include "smu_cmn.h"
-#include "smu_internal.h"
 #include "soc15_common.h"
 
 /*
index e07ff6330c54c182f6a8dea2c6ddb1236db461af..98face8c5fd61b9d0149c0fb94ed76196bdd4bec 100644 (file)
@@ -25,6 +25,7 @@
 
 #include "amdgpu_smu.h"
 
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
                                    enum smu_message_type msg,
                                    uint32_t param,
@@ -79,3 +80,4 @@ int smu_cmn_write_watermarks_table(struct smu_context *smu);
 int smu_cmn_write_pptable(struct smu_context *smu);
 
 #endif
+#endif
index 202e453b4cae2a0b1ac6a7d306bcbdb5513eb12a..2a9ad68c78d222430746cfba8f7e85253cfb28f1 100644 (file)
@@ -25,6 +25,8 @@
 
 #include "amdgpu_smu.h"
 
+#if defined(SWSMU_CODE_LAYER_L1)
+
 #define smu_ppt_funcs(intf, ret, smu, args...) \
        ((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? (smu)->ppt_funcs->intf(smu, ##args) : ret) : -EINVAL)
 
@@ -95,3 +97,4 @@
 #define smu_set_pp_feature_mask(smu, new_mask)                         smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
 
 #endif
+#endif
index 5b77ed8ea14d2a0096b423f95e690d2f4079f4bc..fd82402065e638504830f8816fb906f2115909d4 100644 (file)
 #include <linux/reboot.h>
 
 #define SMU_11_0_PARTIAL_PPTABLE
+#define SWSMU_CODE_LAYER_L3
 
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "amdgpu_atombios.h"
index 7855e8d88af7b5b59d4aa7fab49a25d068995090..31456437bb18e9866f7b61835ba5a88da3e84d04 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#define SWSMU_CODE_LAYER_L3
+
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_smu.h"
-#include "smu_internal.h"
 #include "atomfirmware.h"
 #include "amdgpu_atomfirmware.h"
 #include "smu_v12_0.h"