drm/i915/dp_mst: Enable FEC early once it's known DSC is needed

Enable FEC in crtc_state, as soon as it's known it will be needed by
DSC. This fixes the calculation of BW allocation overhead, in case DSC
is enabled by falling back to it during the encoder compute config
phase (vs. enabling FEC due to DSC being enabled on other streams).

v2:
- Enable FEC only in intel_dp_mst_find_vcpi_slots_for_bpp(), since
  only by that will crtc_state->port_clock be set, which in turn is
  needed by intel_dp_is_uhbr().

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-11-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ea97db7d9abf71e498f321196ceca5e59cd68594..516671f50b6c486a0c9778ac3fae0065d34ee79e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1369,9 +1369,9 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
        return false;
 }
 
-static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
-                                 const struct intel_connector *connector,
-                                 const struct intel_crtc_state *pipe_config)
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+                          const struct intel_connector *connector,
+                          const struct intel_crtc_state *pipe_config)
 {
        return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
                drm_dp_sink_supports_fec(connector->dp.fec_capability);

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 484aea215a251294d4494ea0782942c14a215b4d..0258580a6aadcc2f2a26835aa62bfeb662697c16 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -137,6 +137,11 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 }
 
 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
+
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+                          const struct intel_connector *connector,
+                          const struct intel_crtc_state *pipe_config);
+
 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
 
 void intel_ddi_update_pipe(struct intel_atomic_state *state,

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 6f9c9f3b5b12131b22ffda20d8c33e258169b5a9..28db1775d3a5d2a50b84f3b88721c939c30ae41f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -95,6 +95,13 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
        crtc_state->lane_count = limits->max_lane_count;
        crtc_state->port_clock = limits->max_rate;
 
+       if (dsc) {
+               if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
+                       return -EINVAL;
+
+               crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
+       }
+
        mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
                                                      crtc_state->port_clock,
                                                      crtc_state->lane_count);