clk: mediatek: add pcw_chg_bit control for PLLs of MT7988

Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 513ab6b1b32292258183e7386418b78a13981b29..ce453e1718e5357e992d590fa174cbd1f061d5e1 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -23,7 +23,7 @@
 #define CON0_BASE_EN           BIT(0)
 #define CON0_PWR_ON            BIT(0)
 #define CON0_ISO_EN            BIT(1)
-#define PCW_CHG_MASK           BIT(31)
+#define PCW_CHG_BIT            31
 
 #define AUDPLL_TUNER_EN                BIT(31)
 
@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
                        pll->data->pcw_shift);
        val |= pcw << pll->data->pcw_shift;
        writel(val, pll->pcw_addr);
-       chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
+       chg = readl(pll->pcw_chg_addr) |
+             BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
        writel(chg, pll->pcw_chg_addr);
        if (pll->tuner_addr)
                writel(val + 1, pll->tuner_addr);

diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index f17278ff15d78f124cae44688dc2d29b2e4e4cdb..285c8db958b39e4cd30fe76f41a091806da9839e 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -48,6 +48,7 @@ struct mtk_pll_data {
        const char *parent_name;
        u32 en_reg;
        u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
+       u8 pcw_chg_bit;
 };
 
 /*