arm64: dts: juno: Enable more SMMUs
authorRobin Murphy <robin.murphy@arm.com>
Fri, 5 Mar 2021 17:33:18 +0000 (17:33 +0000)
committerSudeep Holla <sudeep.holla@arm.com>
Mon, 15 Mar 2021 13:24:09 +0000 (13:24 +0000)
Now that PCI inbound window restrictions are handled generically between
the of_pci resource parsing and the IOMMU layer, and described in the
Juno DT, we can finally enable the PCIe SMMU without the risk of DMA
mappings inadvertently allocating unusable addresses.

Similarly, the relevant support for IOMMU mappings for peripheral
transfers has been hooked up in the pl330 driver for ages, so we can
happily enable the DMA SMMU without that breaking anything either.

Link: https://lore.kernel.org/r/a730070d718cb119f77c8ca1782a0d4189bfb3e7.1614965598.git.robin.murphy@arm.com
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
arch/arm64/boot/dts/arm/juno-base.dtsi
arch/arm64/boot/dts/arm/juno-r1.dts
arch/arm64/boot/dts/arm/juno-r2.dts

index b48a76b100b1d073a47badde12642a21fbcb3e33..1cc7fdcec51bccd2dfb74305c65f2f7557980c61 100644 (file)
                #iommu-cells = <1>;
                #global-interrupts = <1>;
                dma-coherent;
-               status = "disabled";
        };
 
        smmu_hdlcd1: iommu@7fb10000 {
index 5f290090b0cf27852338108aedce111c17e902ce..0e24e29eb9b1bc69b9dae27d5b0e746482c284a4 100644 (file)
        status = "okay";
 };
 
+&smmu_pcie {
+       status = "okay";
+};
+
 &etm0 {
        cpu = <&A57_0>;
 };
index 305300dd521c9d4f6c22b9436cd55bd3e811c768..e609420ce3e4e48263ae905c8c04f647b2e51289 100644 (file)
        status = "okay";
 };
 
+&smmu_pcie {
+       status = "okay";
+};
+
 &etm0 {
        cpu = <&A72_0>;
 };