arm64: dts: mt8186: Add power domains controller

Add power domains controller for mt8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Link: https://lore.kernel.org/r/20221123135531.23221-3-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c326aeb33a109f9f846dc721212bd9e4deef51a1..2b03a342b8db8bba4463290b338587e6e67352e6 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -332,6 +332,194 @@
                        #interrupt-cells = <2>;
                };
 
+               scpsys: syscon@10006000 {
+                       compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
+                       reg = <0 0x10006000 0 0x1000>;
+
+                       /* System Power Manager */
+                       spm: power-controller {
+                               compatible = "mediatek,mt8186-power-controller";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #power-domain-cells = <1>;
+
+                               /* power domain of the SoC */
+                               mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
+                                       reg = <MT8186_POWER_DOMAIN_MFG0>;
+                                       clocks = <&topckgen CLK_TOP_MFG>;
+                                       clock-names = "mfg00";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       #power-domain-cells = <1>;
+
+                                       power-domain@MT8186_POWER_DOMAIN_MFG1 {
+                                               reg = <MT8186_POWER_DOMAIN_MFG1>;
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #power-domain-cells = <1>;
+
+                                               power-domain@MT8186_POWER_DOMAIN_MFG2 {
+                                                       reg = <MT8186_POWER_DOMAIN_MFG2>;
+                                                       #power-domain-cells = <0>;
+                                               };
+
+                                               power-domain@MT8186_POWER_DOMAIN_MFG3 {
+                                                       reg = <MT8186_POWER_DOMAIN_MFG3>;
+                                                       #power-domain-cells = <0>;
+                                               };
+                                       };
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
+                                       reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
+                                       clocks = <&topckgen CLK_TOP_SENINF>,
+                                                <&topckgen CLK_TOP_SENINF1>;
+                                       clock-names = "csirx_top0", "csirx_top1";
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_SSUSB {
+                                       reg = <MT8186_POWER_DOMAIN_SSUSB>;
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
+                                       reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
+                                       reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
+                                       clocks = <&topckgen CLK_TOP_AUDIODSP>,
+                                                <&topckgen CLK_TOP_ADSP_BUS>;
+                                       clock-names = "audioadsp", "adsp_bus";
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       #power-domain-cells = <1>;
+
+                                       power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
+                                               reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #power-domain-cells = <1>;
+
+                                               power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
+                                                       reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
+                                                       mediatek,infracfg = <&infracfg_ao>;
+                                                       #power-domain-cells = <0>;
+                                               };
+                                       };
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_CONN_ON {
+                                       reg = <MT8186_POWER_DOMAIN_CONN_ON>;
+                                       mediatek,infracfg = <&infracfg_ao>;
+                                       #power-domain-cells = <0>;
+                               };
+
+                               power-domain@MT8186_POWER_DOMAIN_DIS {
+                                       reg = <MT8186_POWER_DOMAIN_DIS>;
+                                       clocks = <&topckgen CLK_TOP_DISP>,
+                                                <&topckgen CLK_TOP_MDP>,
+                                                <&mmsys CLK_MM_SMI_INFRA>,
+                                                <&mmsys CLK_MM_SMI_COMMON>,
+                                                <&mmsys CLK_MM_SMI_GALS>,
+                                                <&mmsys CLK_MM_SMI_IOMMU>;
+                                       clock-names = "disp", "mdp", "smi_infra", "smi_common",
+                                                    "smi_gals", "smi_iommu";
+                                       mediatek,infracfg = <&infracfg_ao>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       #power-domain-cells = <1>;
+
+                                       power-domain@MT8186_POWER_DOMAIN_VDEC {
+                                               reg = <MT8186_POWER_DOMAIN_VDEC>;
+                                               clocks = <&topckgen CLK_TOP_VDEC>,
+                                                        <&vdecsys CLK_VDEC_LARB1_CKEN>;
+                                               clock-names = "vdec0", "larb";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #power-domain-cells = <0>;
+                                       };
+
+                                       power-domain@MT8186_POWER_DOMAIN_CAM {
+                                               reg = <MT8186_POWER_DOMAIN_CAM>;
+                                               clocks = <&topckgen CLK_TOP_CAM>,
+                                                        <&topckgen CLK_TOP_SENINF>,
+                                                        <&topckgen CLK_TOP_SENINF1>,
+                                                        <&topckgen CLK_TOP_SENINF2>,
+                                                        <&topckgen CLK_TOP_SENINF3>,
+                                                        <&topckgen CLK_TOP_CAMTM>,
+                                                        <&camsys CLK_CAM2MM_GALS>;
+                                               clock-names = "cam-top", "cam0", "cam1", "cam2",
+                                                            "cam3", "cam-tm", "gals";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #power-domain-cells = <1>;
+
+                                               power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
+                                                       reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
+                                                       #power-domain-cells = <0>;
+                                               };
+
+                                               power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
+                                                       reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
+                                                       #power-domain-cells = <0>;
+                                               };
+                                       };
+
+                                       power-domain@MT8186_POWER_DOMAIN_IMG {
+                                               reg = <MT8186_POWER_DOMAIN_IMG>;
+                                               clocks = <&topckgen CLK_TOP_IMG1>,
+                                                        <&imgsys1 CLK_IMG1_GALS_IMG1>;
+                                               clock-names = "img-top", "gals";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #power-domain-cells = <1>;
+
+                                               power-domain@MT8186_POWER_DOMAIN_IMG2 {
+                                                       reg = <MT8186_POWER_DOMAIN_IMG2>;
+                                                       #power-domain-cells = <0>;
+                                               };
+                                       };
+
+                                       power-domain@MT8186_POWER_DOMAIN_IPE {
+                                               reg = <MT8186_POWER_DOMAIN_IPE>;
+                                               clocks = <&topckgen CLK_TOP_IPE>,
+                                                        <&ipesys CLK_IPE_LARB19>,
+                                                        <&ipesys CLK_IPE_LARB20>,
+                                                        <&ipesys CLK_IPE_SMI_SUBCOM>,
+                                                        <&ipesys CLK_IPE_GALS_IPE>;
+                                               clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
+                                                             "ipe-smi", "ipe-gals";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #power-domain-cells = <0>;
+                                       };
+
+                                       power-domain@MT8186_POWER_DOMAIN_VENC {
+                                               reg = <MT8186_POWER_DOMAIN_VENC>;
+                                               clocks = <&topckgen CLK_TOP_VENC>,
+                                                        <&vencsys CLK_VENC_CKE1_VENC>;
+                                               clock-names = "venc0", "larb";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #power-domain-cells = <0>;
+                                       };
+
+                                       power-domain@MT8186_POWER_DOMAIN_WPE {
+                                               reg = <MT8186_POWER_DOMAIN_WPE>;
+                                               clocks = <&topckgen CLK_TOP_WPE>,
+                                                        <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
+                                                        <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
+                                               clock-names = "wpe0", "larb-ck", "larb-pclk";
+                                               mediatek,infracfg = <&infracfg_ao>;
+                                               #power-domain-cells = <0>;
+                                       };
+                               };
+                       };
+               };
+
                watchdog: watchdog@10007000 {
                        compatible = "mediatek,mt8186-wdt",
                                     "mediatek,mt6589-wdt";