/* imx6q/dl does not have cap_1 register, fake one */
                                val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
                                        | SDHCI_SUPPORT_SDR50
-                                       | SDHCI_USE_SDR50_TUNING;
+                                       | SDHCI_USE_SDR50_TUNING
+                                       | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
 
                        if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
                                val |= SDHCI_SUPPORT_HS400;
                writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
                if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
                        new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
-                       if (val & SDHCI_CTRL_TUNED_CLK)
+                       if (val & SDHCI_CTRL_TUNED_CLK) {
                                new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
-                       else
+                               new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
+                       } else {
                                new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
+                               new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
+                       }
                        writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
                } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
                        u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 
        reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
        reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
+       reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
        writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 }