ARM: dts: sunxi: Fix DE2 clocks register range
authorJernej Skrabec <jernej.skrabec@siol.net>
Fri, 24 Jan 2020 23:20:09 +0000 (00:20 +0100)
committerChen-Yu Tsai <wens@csie.org>
Wed, 11 Mar 2020 16:24:29 +0000 (00:24 +0800)
As it can be seen from DE2 manual, clock range is 0x10000.

Fix it.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Fixes: 73f122c82775 ("ARM: dts: sun8i: a83t: Add display pipeline")
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Fixes: 21b299209330 ("ARM: sun8i: v3s: add device nodes for DE2 display pipeline")
Fixes: d8c6f1f0295c ("ARM: sun8i: h3/h5: add DE2 CCU device node for H3")
[wens@csie.org: added fixes tags]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
arch/arm/boot/dts/sun8i-a83t.dtsi
arch/arm/boot/dts/sun8i-r40.dtsi
arch/arm/boot/dts/sun8i-v3s.dtsi
arch/arm/boot/dts/sunxi-h3-h5.dtsi

index 53c2b6a836f273d8d57c924ae612d15c6c38be25..92c69534d1e514732f95d323bc6d358fa6d8d153 100644 (file)
 
                display_clocks: clock@1000000 {
                        compatible = "allwinner,sun8i-a83t-de2-clk";
-                       reg = <0x01000000 0x100000>;
+                       reg = <0x01000000 0x10000>;
                        clocks = <&ccu CLK_BUS_DE>,
                                 <&ccu CLK_PLL_DE>;
                        clock-names = "bus",
index d5442b5b6fd2277bc4c65bb2df8a9ca4ff4d0fb7..b2dd00a8eb9d5b5dc0bc10ed2915feaaa89ecda0 100644 (file)
                display_clocks: clock@1000000 {
                        compatible = "allwinner,sun8i-r40-de2-clk",
                                     "allwinner,sun8i-h3-de2-clk";
-                       reg = <0x01000000 0x100000>;
+                       reg = <0x01000000 0x10000>;
                        clocks = <&ccu CLK_BUS_DE>,
                                 <&ccu CLK_DE>;
                        clock-names = "bus",
index 81ea50838cd5697115c0bb126feb35f2e75cbbd9..e5312869c0d2a48332780d80100e1e70706a7d98 100644 (file)
 
                display_clocks: clock@1000000 {
                        compatible = "allwinner,sun8i-v3s-de2-clk";
-                       reg = <0x01000000 0x100000>;
+                       reg = <0x01000000 0x10000>;
                        clocks = <&ccu CLK_BUS_DE>,
                                 <&ccu CLK_DE>;
                        clock-names = "bus",
index ed39088491110428c31ef3fdbdfd0a7df33f2cc6..d5516019e0f6ea17aec7f52ab165b16049a33bca 100644 (file)
 
                display_clocks: clock@1000000 {
                        /* compatible is in per SoC .dtsi file */
-                       reg = <0x01000000 0x100000>;
+                       reg = <0x01000000 0x10000>;
                        clocks = <&ccu CLK_BUS_DE>,
                                 <&ccu CLK_DE>;
                        clock-names = "bus",