powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB

Pinned TLB are 8M. Now that there is no strict boundary anymore
between text and RO data, it is possible to use 8M pinned executable
TLB that covers both text and RO data.

When PIN_TLB_DATA or PIN_TLB_TEXT is selected, enforce 8M RW data
alignment and allow STRICT_KERNEL_RWX.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c535fc97bf0dd8693192e25feeed8088701e00c6.1589866984.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index d147d379b1b9361a0f74f9d05168ba796dfccb50..f5e82629e2cd94ec498ddb09c6e97916f4b4ab78 100644 (file)
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -779,9 +779,10 @@ config THREAD_SHIFT
          want. Only change this if you know what you are doing.
 
 config DATA_SHIFT_BOOL
-       bool "Set custom data alignment" if STRICT_KERNEL_RWX && \
-                                           (PPC_BOOK3S_32 || PPC_8xx)
+       bool "Set custom data alignment"
        depends on ADVANCED_OPTIONS
+       depends on STRICT_KERNEL_RWX
+       depends on PPC_BOOK3S_32 || (PPC_8xx && !PIN_TLB_DATA && !PIN_TLB_TEXT)
        help
          This option allows you to set the kernel data alignment. When
          RAM is mapped by blocks, the alignment needs to fit the size and
@@ -803,7 +804,8 @@ config DATA_SHIFT
 
          On 8xx, large pages (512kb or 8M) are used to map kernel linear
          memory. Aligning to 8M reduces TLB misses as only 8M pages are used
-         in that case.
+         in that case. If PIN_TLB is selected, it must be aligned to 8M as
+         8M pages will be pinned.
 
 config FORCE_MAX_ZONEORDER
        int "Maximum zone order"

diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index ec3ef75895d8c5017ed22f5c2a5ca4f109535bdc..d8697f535c3e958154e3da3b578eb0adc57822c9 100644 (file)
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -127,8 +127,8 @@ void __init mmu_mapin_immr(void)
                                    PAGE_KERNEL_NCG, MMU_PAGE_512K, true);
 }
 
-static void __init mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,
-                                      pgprot_t prot, bool new)
+static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,
+                               pgprot_t prot, bool new)
 {
        unsigned long v = PAGE_OFFSET + offset;
        unsigned long p = offset;
@@ -181,6 +181,9 @@ void mmu_mark_initmem_nx(void)
 
        mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, false);
        mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false);
+
+       if (IS_ENABLED(CONFIG_PIN_TLB_TEXT))
+               mmu_pin_tlb(block_mapped_ram, false);
 }
 
 #ifdef CONFIG_STRICT_KERNEL_RWX
@@ -189,6 +192,8 @@ void mmu_mark_rodata_ro(void)
        unsigned long sinittext = __pa(_sinittext);
 
        mmu_mapin_ram_chunk(0, sinittext, PAGE_KERNEL_ROX, false);
+       if (IS_ENABLED(CONFIG_PIN_TLB_DATA))
+               mmu_pin_tlb(block_mapped_ram, true);
 }
 #endif
 

diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 04ea1a8a0bdc8e1947eb66b27f90beb8d461968c..05669f2fadce924ec2702928114f4a9d0fee18a4 100644 (file)
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -167,7 +167,7 @@ menu "8xx advanced setup"
 
 config PIN_TLB
        bool "Pinned Kernel TLBs"
-       depends on ADVANCED_OPTIONS && !DEBUG_PAGEALLOC && !STRICT_KERNEL_RWX
+       depends on ADVANCED_OPTIONS && !DEBUG_PAGEALLOC
        help
          On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
          table 4 TLBs can be pinned.