arm64: dts: qcom: sdm845-mtp: enable PCIe support

Enable two PCIe hosts support on Qualcomm SDM845 MTP board.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230826221915.846937-6-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index aec3f358d426c79f569ff873eb2e095311d59eaf..76bfa786612c7e72fd7da3bdecd2237df18577ad 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -533,6 +533,38 @@
        firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
 };
 
+&pcie0 {
+       perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+
+       pinctrl-0 = <&pcie0_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie0_phy {
+       vdda-phy-supply = <&vreg_l1a_0p875>;
+       vdda-pll-supply = <&vreg_l26a_1p2>;
+
+       status = "okay";
+};
+
+&pcie1 {
+       perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_default_state>;
+
+       status = "okay";
+};
+
+&pcie1_phy {
+       status = "okay";
+
+       vdda-phy-supply = <&vreg_l1a_0p875>;
+       vdda-pll-supply = <&vreg_l26a_1p2>;
+};
+
 &pm8998_adc {
        channel@4c {
                reg = <ADC5_XO_THERM_100K_PU>;
@@ -630,6 +662,52 @@
        cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
 };
 
+&tlmm {
+       pcie0_default_state: pcie0-default-state {
+               clkreq-pins {
+                       pins = "gpio36";
+                       function = "pci_e0";
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio35";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio37";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie1_default_state: pcie1-default-state {
+               clkreq-pins {
+                       pins = "gpio103";
+                       function = "pci_e1";
+                       bias-pull-up;
+               };
+
+               perst-n-pins {
+                       pins = "gpio102";
+                       function = "gpio";
+                       drive-strength = <16>;
+                       bias-pull-down;
+               };
+
+               wake-n-pins {
+                       pins = "gpio104";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+};
+
 &uart9 {
        status = "okay";
 };