ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers

Now that the pinctrl definitions of the ast2600 SoC have been fixed,
see commit 925fbe1f7eb6 ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI
function/group"), it is safe to activate QSPI on the ast2600 evb.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 14dbeaee7ee335d778e4588619d6ce65ef151f0f..5c6eacb43c03fad5f24136f6e8a65e3c07a32a0c 100644 (file)
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -182,6 +182,7 @@
                status = "okay";
                m25p,fast-read;
                label = "bmc";
+               spi-rx-bus-width = <4>;
                spi-max-frequency = <50000000>;
 #include "openbmc-flash-layout-64.dtsi"
        };
@@ -196,6 +197,7 @@
                status = "okay";
                m25p,fast-read;
                label = "pnor";
+               spi-rx-bus-width = <4>;
                spi-max-frequency = <100000000>;
        };
 };