arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox

While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-11-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 5a71cfccb8e0dbcdc84679a63d595ce9e3b9a761..42e2e48b2bc3d10591eed3b4dbe43cecb6ce22be 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -403,8 +403,8 @@
                                     "qcom,ipq6018-apcs-apps-global";
                        reg = <0x0b111000 0x1000>;
                        #clock-cells = <1>;
-                       clocks = <&a53pll>, <&xo_board>;
-                       clock-names = "pll", "xo";
+                       clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
+                       clock-names = "pll", "xo", "gpll0";
                        #mbox-cells = <1>;
                };