drm/amdgpu: Enable TCP channel hashing for Aldebaran

Enable TCP channel hashing to match DF hash settings for Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 0d8459d63bac172a3710f6448e233657c2676fe7..36ba229576d83d147ae5935cfdffcd333e2865ad 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -219,11 +219,11 @@ static void df_v3_6_query_hashes(struct amdgpu_device *adev)
        adev->df.hash_status.hash_2m = false;
        adev->df.hash_status.hash_1g = false;
 
-       if (adev->asic_type != CHIP_ARCTURUS)
-               return;
-
-       /* encoding for hash-enabled on Arcturus */
-       if (adev->df.funcs->get_fb_channel_number(adev) == 0xe) {
+       /* encoding for hash-enabled on Arcturus and Aldebaran */
+       if ((adev->asic_type == CHIP_ARCTURUS &&
+            adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||
+            (adev->asic_type == CHIP_ALDEBARAN &&
+             adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {
                tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
                adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
                                                DF_CS_UMC_AON0_DfGlobalCtrl,
@@ -278,7 +278,12 @@ static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
        u32 tmp;
 
        tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
-       tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+       if (adev->asic_type == CHIP_ALDEBARAN)
+               tmp &=
+               ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+       else
+               tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+
        tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
 
        return tmp;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 16a3b279a9ef9000a7aaf35fa0dd4171eb100978..22608c45f07c3fad915b298e8eeb3cfda4b4859c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3937,7 +3937,8 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
 {
        u32 tmp;
 
-       if (adev->asic_type != CHIP_ARCTURUS)
+       if (adev->asic_type != CHIP_ARCTURUS &&
+           adev->asic_type != CHIP_ALDEBARAN)
                return;
 
        tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);

diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
index 7afa87c7ff5437d875182a552b9e1a928a38bd92..f804e13b002e97cb749e976c6c900244920e6fd6 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
@@ -50,6 +50,7 @@
 #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK                                               0x00000001L
 #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                           0x00000002L
 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK                                             0x0000003CL
+#define ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK                                   0x0000007CL
 #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                             0x00000E00L
 #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK                                             0xFFFFF000L