li      r5, 0
        li      r6, 0
        li      r7, 0
-       ld      r11,opal@got(r2)
+       LOAD_REG_ADDR(r11, opal)
        ld      r8,0(r11)
        ld      r9,8(r11)
        bctr
        mr      r13,r2
 
        /* Set opal return address */
-       ld      r11,opal_return@got(r2)
+       LOAD_REG_ADDR(r11, opal_return)
        mtlr    r11
        mfmsr   r12
 
        mtspr   SPRN_HSRR1,r12
 
        /* load the opal call entry point and base */
-       ld      r11,opal@got(r2)
+       LOAD_REG_ADDR(r11, opal)
        ld      r12,8(r11)
        ld      r2,0(r11)
        mtspr   SPRN_HSRR0,r12
 
 #define MFTBU(dest)                    mfspr dest, SPRN_TBRU
 #endif
 
+#ifdef CONFIG_PPC64_BOOT_WRAPPER
+#define LOAD_REG_ADDR(reg,name)                        \
+       ld      reg,name@got(r2)
+#else
+#define LOAD_REG_ADDR(reg,name)                        \
+       lis     reg,name@ha;                    \
+       addi    reg,reg,name@l
+#endif
+
 #endif /* _PPC64_PPC_ASM_H */
 
 swsusp_save_area:
        .space SL_SIZE
 
-       .section ".toc","aw"
-swsusp_save_area_ptr:
-       .tc     swsusp_save_area[TC],swsusp_save_area
-restore_pblist_ptr:
-       .tc     restore_pblist[TC],restore_pblist
-
        .section .text
        .align  5
 _GLOBAL(swsusp_arch_suspend)
-       ld      r11,swsusp_save_area_ptr@toc(r2)
+       LOAD_REG_ADDR(r11, swsusp_save_area)
        SAVE_SPECIAL(LR)
        SAVE_REGISTER(r1)
        SAVE_SPECIAL(CR)
        bl swsusp_save
 
        /* restore LR */
-       ld      r11,swsusp_save_area_ptr@toc(r2)
+       LOAD_REG_ADDR(r11, swsusp_save_area)
        RESTORE_SPECIAL(LR)
        addi    r1,r1,128
 
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        sync
 
-       ld      r12,restore_pblist_ptr@toc(r2)
+       LOAD_REG_ADDR(r11, restore_pblist)
        ld      r12,0(r12)
 
        cmpdi   r12,0
        tlbia
 #endif
 
-       ld      r11,swsusp_save_area_ptr@toc(r2)
+       LOAD_REG_ADDR(r11, swsusp_save_area)
 
        RESTORE_SPECIAL(CR)
 
        bl      do_after_copyback
        addi    r1,r1,128
 
-       ld      r11,swsusp_save_area_ptr@toc(r2)
+       LOAD_REG_ADDR(r11, swsusp_save_area)
        RESTORE_SPECIAL(LR)
 
        li      r3, 0
 
        std     r2, STK_GOT(r1)
        ld      r2,PACATOC(r13) /* get kernel TOC in r2 */
 
-       addis   r3,r2,function_trace_op@toc@ha
-       addi    r3,r3,function_trace_op@toc@l
+       LOAD_REG_ADDR(r3, function_trace_op)
        ld      r5,0(r3)
 #else
        lis     r3,function_trace_op@ha
 
  * usage of floating-point registers.  These routines must be called
  * with preempt disabled.
  */
-#ifdef CONFIG_PPC32
        .data
+#ifdef CONFIG_PPC32
 fpzero:
        .long   0
 fpone:
        lfs     fr,name@l(r11)
 #else
 
-       .section ".toc","aw"
 fpzero:
-       .tc     FD_0_0[TC],0
+       .quad   0
 fpone:
-       .tc     FD_3ff00000_0[TC],0x3ff0000000000000    /* 1.0 */
+       .quad   0x3ff0000000000000      /* 1.0 */
 fphalf:
-       .tc     FD_3fe00000_0[TC],0x3fe0000000000000    /* 0.5 */
+       .quad   0x3fe0000000000000      /* 0.5 */
 
-#define LDCONST(fr, name)      \
-       lfd     fr,name@toc(r2)
+#define LDCONST(fr, name)              \
+       addis   r11,r2,name@toc@ha;     \
+       lfd     fr,name@toc@l(r11)
 #endif
-
        .text
 /*
  * Internal routine to enable floating point and set FPSCR to 0.
 
 #include <asm/export.h>
 #include <asm/feature-fixups.h>
 
-        .section        ".toc","aw"
-PPC64_CACHES:
-        .tc             ppc64_caches[TC],ppc64_caches
-        .section        ".text"
-
 _GLOBAL_TOC(copy_page)
 BEGIN_FTR_SECTION
        lis     r5,PAGE_SIZE@h
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
        ori     r5,r5,PAGE_SIZE@l
 BEGIN_FTR_SECTION
-       ld      r10,PPC64_CACHES@toc(r2)
+       LOAD_REG_ADDR(r10, ppc64_caches)
        lwz     r11,DCACHEL1LOGBLOCKSIZE(r10)   /* log2 of cache block size */
        lwz     r12,DCACHEL1BLOCKSIZE(r10)      /* get cache block size */
        li      r9,0
 
 #include <asm/asm-offsets.h>
 #include <asm/export.h>
 
-       .section        ".toc","aw"
-PPC64_CACHES:
-       .tc             ppc64_caches[TC],ppc64_caches
-       .section        ".text"
-
 /**
  * __arch_clear_user: - Zero a block of memory in user space, with less checking.
  * @to:   Destination address, in user space.
        blr
 
 .Llong_clear:
-       ld      r5,PPC64_CACHES@toc(r2)
+       LOAD_REG_ADDR(r5, ppc64_caches)
 
        bf      cr7*4+0,11f
 err2;  std     r0,0(r3)
 
 _GLOBAL(read_bhrb)
        cmpldi  r3,31
        bgt     1f
-       ld      r4,bhrb_table@got(r2)
+       LOAD_REG_ADDR(r4, bhrb_table)
        sldi    r3,r3,3
        add     r3,r4,r3
        mtctr   r3
 
 
 /* unsigned long xmon_mfspr(sprn, default_value) */
 _GLOBAL(xmon_mfspr)
-       PPC_LL  r5, .Lmfspr_table@got(r2)
+       LOAD_REG_ADDR(r5, .Lmfspr_table)
        b       xmon_mxspr
 
 /* void xmon_mtspr(sprn, new_value) */
 _GLOBAL(xmon_mtspr)
-       PPC_LL  r5, .Lmtspr_table@got(r2)
+       LOAD_REG_ADDR(r5, .Lmtspr_table)
        b       xmon_mxspr
 
 /*