};
 EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_cml_machines);
 
+static const u64 rt711_0_adr[] = {
+       0x000010025D071100
+};
+
+static const u64 rt1308_1_adr[] = {
+       0x000110025D130800
+};
+
+static const u64 rt1308_2_adr[] = {
+       0x000210025D130800
+};
+
+static const u64 rt715_3_adr[] = {
+       0x000310025D071500
+};
+
+static const struct snd_soc_acpi_link_adr cml_3_in_1_default[] = {
+       {
+               .mask = BIT(0),
+               .num_adr = ARRAY_SIZE(rt711_0_adr),
+               .adr = rt711_0_adr,
+       },
+       {
+               .mask = BIT(1),
+               .num_adr = ARRAY_SIZE(rt1308_1_adr),
+               .adr = rt1308_1_adr,
+       },
+       {
+               .mask = BIT(2),
+               .num_adr = ARRAY_SIZE(rt1308_2_adr),
+               .adr = rt1308_2_adr,
+       },
+       {
+               .mask = BIT(3),
+               .num_adr = ARRAY_SIZE(rt715_3_adr),
+               .adr = rt715_3_adr,
+       },
+       {}
+};
+
+static const struct snd_soc_acpi_link_adr cml_3_in_1_mono_amp[] = {
+       {
+               .mask = BIT(0),
+               .num_adr = ARRAY_SIZE(rt711_0_adr),
+               .adr = rt711_0_adr,
+       },
+       {
+               .mask = BIT(1),
+               .num_adr = ARRAY_SIZE(rt1308_1_adr),
+               .adr = rt1308_1_adr,
+       },
+       {
+               .mask = BIT(3),
+               .num_adr = ARRAY_SIZE(rt715_3_adr),
+               .adr = rt715_3_adr,
+       },
+       {}
+};
+
+struct snd_soc_acpi_mach snd_soc_acpi_intel_cml_sdw_machines[] = {
+       {
+               .link_mask = 0xF, /* 4 active links required */
+               .links = cml_3_in_1_default,
+               .drv_name = "sdw_rt711_rt1308_rt715",
+               .sof_fw_filename = "sof-cml.ri",
+               .sof_tplg_filename = "sof-cml-rt711-rt1308-rt715.tplg",
+       },
+       {
+               /*
+                * link_mask should be 0xB, but all links are enabled by BIOS.
+                * This entry will be selected if there is no rt1308 exposed
+                * on link2 since it will fail to match the above entry.
+                */
+               .link_mask = 0xF,
+               .links = cml_3_in_1_mono_amp,
+               .drv_name = "sdw_rt711_rt1308_rt715",
+               .sof_fw_filename = "sof-cml.ri",
+               .sof_tplg_filename = "sof-cml-rt711-rt1308-mono-rt715.tplg",
+       },
+       {
+               .link_mask = 0x2, /* RT700 connected on Link1 */
+               .drv_name = "sdw_rt700",
+               .sof_fw_filename = "sof-cml.ri",
+               .sof_tplg_filename = "sof-cml-rt700.tplg",
+       },
+       {}
+};
+EXPORT_SYMBOL_GPL(snd_soc_acpi_intel_cml_sdw_machines);
+
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("Intel Common ACPI Match module");